79RC32K438-233BB IDT, 79RC32K438-233BB Datasheet - Page 35
79RC32K438-233BB
Manufacturer Part Number
79RC32K438-233BB
Description
Processors - Application Specialized
Manufacturer
IDT
Datasheet
1.79RC32K438-233BBG.pdf
(59 pages)
Specifications of 79RC32K438-233BB
Part # Aliases
IDT79RC32K438-233BB
- Current page: 35 of 59
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EJTAG and JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
EJTAG_TMS
VSENSE
1.
2.
IDT 79RC32438
The values for this symbol were determined by calculation, not by testing.
The JTAG specification, IEEE 1149.1, recommends that both JTAG_TMS and EJTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1.
Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when either JTAG_TMS or EJTAG_TMS is low, because the
TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Signal
1
,
1
Tper_16a
Thigh_16a,
Tlow_16a
Tsu_16b
Thld_16b
Tdo_16c
Tdz_16c
Tpw_16d
Tsu_16e
Thld_6e
Trise_16f
Symbol
2
2
none
JTAG_TCK
JTAG_TCK
falling
none
JTAG_TCK
rising
none
Reference
rising
Edge
25.0
10.0
25.0
200MHz
Min
2.4
1.0
2.0
1.0
—
—
—
Table 14 JTAG AC Timing Characteristics
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
2
25.0
10.0
25.0
233MHz
Min
2.4
1.0
2.0
1.0
—
—
—
35 of 59
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
2
25.0
10.0
25.0
266MHz
Min
2.4
1.0
2.0
1.0
—
—
—
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
2
25.0
300MHz
10.0
25.0
Min
2.4
1.0
2.0
1.0
—
—
—
Max
50.0
25.0
11.3
11.3
—
—
—
—
—
2
Unit Conditions
sec
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured from
0.5V (T
active
)
May 25, 2004
See Figure 22.
See Figure 24.
Reference
Diagram
Timing
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