MC35XS3500DHFKR2 Freescale Semiconductor, MC35XS3500DHFKR2 Datasheet - Page 4

• Manufacturer Part Number: MC35XS3500DHFKR2
• Description: Power Switch ICs - Power Distribution PENTA 35MOHM ESWITCH
• Manufacturer: Freescale Semiconductor

Specifications of MC35XS3500DHFKR2

• Rohs: yes
• Number Of Outputs: 5
• On Resistance (max): 35 mOhms
• Operating Supply Voltage: 7 V to 20 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: PQFN-24
• Minimum Operating Temperature: - 40 C
• Output Current: 65 mA

Table 2. 35XS3500 Pin Definitions
4
35XS3500
PIN CONNECTIONS
Functional descriptions these pins can be found in the
Pin
1
2
3
4
5
6
7
8
Pin Name
FLASHER
CLOCK
FETIN
STOP
LIMP
RST
IGN
CS
Figure 3. 35XS3500 Pin Connections (Transparent Package Top View)
Pin Function
Input
Input
Input
Input
Input
Input
Input
Input
OUT5
GND
CP
13
External FET Input
16
17
18
Limp Home Input
Stop Light Input
Formal Name
12
Flasher Input
Ignition Input
(Active High)
(Active High)
(Active High)
(Active High)
OUT4
(Active Low)
Chip Select
Clock Input
19
Reset
11
PIN CONNECTIONS
10
9
Functional Description
8
VBAT
GND
OUT3
This pin is the current sense recopy of the external MOSFET.
This input wakes the device. It also controls outputs 1 and 2 in case of
Fail mode activation. This pin has a passive internal pull-down.
This input wakes the device. It is also used to initialize the device
configuration and fault registers through the SPI. This pin has a passive
internal pull-down.
This input wakes the device. This pin has a passive internal pull-down.
This pin state depends on RST logic level.
As long as RST input pin is set to logic [0], this pin is pulled up in order to
report wake event. Otherwise, the PWM frequency and timing are
generated from this digital clock input by the PWM module.
This pin has a passive internal pull-down.
The Fail mode can be activated by this digital input. This pin has an active
internal pull-down current source.
This input wakes the device. This pin has a passive internal pull-down.
When this signal is high, SPI signals are ignored. Asserting this pin low
starts a SPI transaction. The transaction is signaled as completed when
this signal returns high. This pin has a passive internal pull-up resistance.
14
15
20
7
6
5
4
3
OUT2
section beginning on
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2
24
23
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1
Definition
Analog Integrated Circuit Device Data
CSNS
GND
OUT1
Freescale Semiconductor
page
22.