25AA512-I/SM Microchip Technology, 25AA512-I/SM Datasheet - Page 15
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25AA512-I/SM
Manufacturer Part Number
25AA512-I/SM
Description
IC EEPROM 512KBIT 20MHZ 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.25AA512-ISN.pdf
(36 pages)
Specifications of 25AA512-I/SM
Memory Size
512K (64K x 8)
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
20MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Organization
64 K x 8
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Access Time
250 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
7 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V, 5.5 V
Memory Configuration
64K X 8
Ic Interface Type
SPI
Clock Frequency
20MHz
Supply Voltage Range
1.8V To 5.5V
Memory Case Style
SOIJ
No. Of Pins
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
25AA512-I/SM
Manufacturer:
MICROCHIP
Quantity:
3 300
Company:
Part Number:
25AA512-I/SM
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
25AA512-I/SM
Manufacturer:
MICROCHIP
Quantity:
3 300
Part Number:
25AA512-I/SM
Manufacturer:
MICROCHI
Quantity:
20 000
2.8
The PAGE ERASE instruction will erase all bits (FFh)
inside the given page. A Write Enable (WREN) instruc-
tion must be given prior to attempting a PAGE ERASE.
This is done by setting CS low and then clocking out
the proper instruction into the 25AA512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The PAGE ERASE instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
FIGURE 2-8:
2010 Microchip Technology Inc.
PAGE ERASE
SCK
CS
SO
SI
PAGE ERASE SEQUENCE
1
0
1
1
0
Instruction
2
1
3
1
4
0
5
High-Impedance
0
6
0
7
15 14 13 12
8
9 10 11
CS must then be driven high after the last bit of the
address or the PAGE ERASE will not execute. Once
the CS is driven high the self-timed PAGE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the PAGE ERASE cycle
is complete.
If a PAGE ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
16-bit Address
21 22 23
2
1
0
25AA512
DS22021F-page 15
ERASE