MC20XS4200FK Freescale Semiconductor, MC20XS4200FK Datasheet

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... V and 5.0 V compatible 16-bit SPI port for device control, configuration and diagnostics at rates up to 8.0 MHz V DD SCLK MCU GND * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2012. All rights reserved. MC20XS4200FK 20XS4200 VDD VPWR I/O CLOCK ...

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... Detect. Temperature Feedback GND Figure 2. Internal Block Diagram VPWR Drain/Gate Charge Clamp Pump Selectable Slew Rate Gate Driver HS0 Short-circuit to VPWR detec. Open-load Detect HS0 HS1 HS1 Output Current Sense Analog MUX CSNS SYNC Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Pin Assignment and Functions Functional Internal Block Description Functional Device Operation Operation and Operating Modes Logic Commands and SPI Registers Typical Applications Packaging Soldering Information Package Dimensions Revision History Analog Integrated Circuit Device Data Freescale Semiconductor TABLE OF CONTENTS TABLE OF CONTENTS ...

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... This input pin is connected to the SPI chip-select output of an external micro- Chip Select controller. CSB is internally pulled (Active Low) SYNC GND VPWR Definition Functional Fault Mode current source Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... SYNC Output Output Current Synchronization Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description This input pin connected to an external SPI Clock signal. The SCLK Serial Clock pin is internally connected to a pull-down current source I This input pin receives the SPI input data from an external device (micro- Serial Input controller or another extreme switch device in case of daisy-chaining) ...

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... 150 C initial). PWR J ° 125 C initial, f <2.0 Hz). PWR J S ° 125 C initial, f <2.0 Hz). PWR 1500 Ω), and the Charge Device ZAP Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Analog Integrated Circuit Device Data Freescale Semiconductor Symbol T T ...

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... DS(ON) < before the end of the auto-retry period PWR , under-voltage is detected (see Under-voltage Analog Integrated Circuit Device Data Freescale Semiconductor V μA V μ ...

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... Severe Short-circuit Fault (latchable fault)): High slew rate selected Medium slew rate selected: Low slew rate selected: Over-current Detection thresholds with CSNS_ratio bit = 0 (CSR0) Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° & V ...

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... Activation and Use of Offset Compensation defined above, see SRx , _LOAD_ERR_SYS I / CSR - I = CSNS x _LOAD_ERR_SYS Analog Integrated Circuit Device Data Freescale Semiconductor A µ – µA ...

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... Notes: 16 SRx_ERR CSNS_MEAS CSNS_MODEL section Current Sense Error Model). With this model, load current becomes: I(HS[x]) Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° & PWR Symbol (16) at output ...

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... C (I defined above, see SRx , _LOAD_ERR_SYS I / CSR - I = CSNS x _LOAD_ERR_SYS (see Activation and Use of Offset Compensation OLD(THRES) HS OLD(OFF) Analog Integrated Circuit Device Data Freescale Semiconductor % % % ) ...

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... Switching State (On/Off) discrimination thresholds Shutdown temperature (Power MOSFET junction; 6.0 V < V Notes: 20. Minimum required value of Open-load impedance for detection of Open-load in OFF-state: 200 kΩ.(V Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° & V ...

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... Unit 2.0 – 5.5 -0.3 – 0.8 1.0 – 2.2 5.0 – 20 5.0 – – 100 – – 20 125 250 500 – 4 -0.4 – – DD – – 0.4 - 2.0 0.0 2.0 1.0 – – Infinite ~ 3.0 V). REG Analog Integrated Circuit Device Data Freescale Semiconductor μA μA μA pF kΩ μA kΩ ...

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... HS PWR L Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR °C & V PWR ...

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... Output Voltage Slew Rate PWR ) are defined for a SYNREAD_XX A_0 CSNS_ _ X FOR RATIO S Analog Integrated Circuit Device Data Freescale Semiconductor Unit μs μs μs μs μs μs μs μs μs μs µs µs µ 0). ...

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... Maximal allowed Low Time during Calibration of the Internal Clock through CSB Recommended external Clock Frequency Range (external clock/PWM Module) Upper detection threshold for external Clock frequency monitoring Lower detection threshold for external Clock frequency monitoring Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T PWR ° ...

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... PWR A Symbol t (33) t WDTO t AUTO_00 t AUTO_01 t AUTO_10 t AUTO_11 ≤ 125 °C, GND = 0 V. Typical values are A = 5.0 V, unless specified otherwise. DD Min Typ Max 175 250 325 IN 217 310 400 105 150 195 52.5 75 97.5 26.2 37.5 47.8 13.1 17.7 24.4 Analog Integrated Circuit Device Data Freescale Semiconductor Unit ...

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... For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (V ceramic speed-up capacitors in parallel with the >8.0 kΩ input resistors are required on pins SCLK, SI, SO, CS Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 3.0 V ≤ V ≤ 5 °C ≤ T ...

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... V PWM t t DLY_XX DLY_XX ( DLY(ON) DLY(OFF Bulb profile: CONFs = 0 (V (pin 5/6) <0.8 V). Static over-current protection profile activated once per turn-on. Default levels shown as solid lines Time Time PWR 50%V PWR Time F Time Time Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... ENBL t WRSTB CSB 10 LEAD 90 SCLK 10 90 Don’t Care 10% V Tri-stated SO Figure 7. Timing Requirements During SPI Communication Analog Integrated Circuit Device Data Freescale Semiconductor t OCM2_M t OCM1_M t OCH2 t OCH1 t t RSI WSCLKh t SI(SU) t WSCLKl t SI(H) DD Must be Valid Don’ ...

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... DD 10 turn-on turn-off control control (from IN_s or CSB) (from IN_s or CSB) See Figure 3 ) synchronous Mode t FSI 50%V PWR Time t DLY_XX DLY(OFF Track & Hold Mode Time Time Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... When the current sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to V The CSNS pin can source currents up to about 5.6 mA. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION Current sensing with an adjustable ratio is available on both channels, allowing both high current (bulbs) and low current (LED) monitoring. By activating the Track & ...

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... The device transfers the contents of one is CSB (Figure 7 and Figure 8). through CSB is at logic [1]). When Figure 7), starting with bit D15 Table 13. Register addresses and Table 14. The SI pin is . DWN derived PWR Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor POWER SWITCH OUTPUT PINS (HS0 AND HS1) HS0 and HS1 are the output pins of the power switches connected to the loads. A ceramic capacitor (< (+/ ...

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... Mode). The device is in Normal mode ) are within the normal range and DD 4. (Internal Clock & Internal PWM 1)). Frequency, slew rate, duty-cycle, and /2 and “Off” PWR /2. The channel’s switching state PWR Analog Integrated Circuit Device Data Freescale Semiconductor and ...

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... RSTB . IN[x] IN_ON[x] Figure 10. Relation Between Signals IN(x) and IN_ON[x] Analog Integrated Circuit Device Data Freescale Semiconductor Direct Control Mode When RSTB are merely controlled by the direct input pins IN[x]. All protective functions (OC, OT, SC, OV, and UV) are operational including auto-retry. To avoid entering Sleep mode at frequencies < ...

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... To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained Normal Failure and V _FAIL_en=1 before and WD_dis = 0). = 310 ms typ. WDTO , Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Only the Direct Inputs control the channels. Analog Integrated Circuit Device Data Freescale Semiconductor Returning from Fault Mode to Fail-safe Mode When disappearance of the fault previously produced in Fail- safe mode has been detected, the device returns to Fail-safe mode and behaves accordingly ...

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... PWM clock periods 96 PWM clock periods 128 PWM clock periods 160 PWM clock periods 192 PWM clock periods 224 PWM clock periods Table 6 apply. When an external or f> CLOCK(LOW) module). Calibration of the default reduces it maximum variation from about Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL=1, the contents of the corresponding Analog Integrated Circuit Device Data Freescale Semiconductor registers in bank 1 will be replaced by that of bank 0, except bits D6-D8 of the CONFR_1 register (configuration of the Open-load/Output short-circuited diagnostics recommended to disable the off-state open-load for the HS1 output ...

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... Type of Load resistive: CONF = 0, Lighting-Mode inductive: CONF = 1, DC motor mode ). OCM2_L Window Activity , I and I _OCH _OCM _OCL Figure 5. This profile has The width of the OCH1 OCH2 or t (see Table 17). OCM1_L OCM2_L Analog Integrated Circuit Device Data Freescale Semiconductor , ...

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... Figure 14. Over-current Shutdown in PWM mode (solid line) and Fully-on Mode (dashed line) Analog Integrated Circuit Device Data Freescale Semiconductor Reset of the Duration Counter Reset of the duration counter is achieved by performing a delatch sequence and I ...

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... IN[x] input(s) are tied to V Fail-safe will be entered under the following conditions: Table 3. Coupling V DS( CLA M P K.I z HS[ IMEG Load V CL GND PWR PWR , in case they are connected to PWR (Figure 21 PWR Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... FSB pin. However, without V the SO pin is no longer DD, Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATION AND OPERATING MODES functional. The SPI registers can no longer be read and detailed fault information is unavailable. Current sensing also becomes unavailable wasn’ ...

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... This guarantees a maximum device availability without preventing fault detection. (Open-loadOFF = Latched OFF Auto-retry Loop (Open-loadON = 1) ( Retry_s bit auto-retry 0 enabled 1 disabled 0 disabled 1 enabled ) is set through the SPI AUTO Table Analog Integrated Circuit Device Data Freescale Semiconductor 21). ...

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... Diagnostic functions open-load-in-On state (OLON), open- load-in-Off-state (OLOFF) and output short-circuited to V (OS) are operational over the frequency and duty cycle Analog Integrated Circuit Device Data Freescale Semiconductor ranges specified in values also depend on the way the device is controlled (direct/internal PWM), on the current sense ratio and on the optional activation of the open-load-in-On-state detection ...

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... Table 22) in the (Output Current 17) selected by the CSNS_ratio bit in the 18. The amount of current the CSNS .The CSNS pin must be CSNS,MAX. (SYNC)). After turn-off, the Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Computing the compensated current sensing value is illustrated in the next sections. Analog Integrated Circuit Device Data Freescale Semiconductor Activation and Use of Offset Compensation According to the settings of the OFP_s bit (in the RETRYR_s register), opposite values of the random offset error are generated ...

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... It withstands electric fields up to 200 V/m and Bulk Current Injection (BCI 200 mA per ISO11452. The device meets Class 5 of the CISPR25 emission standard. (pin #14, OTWAR . OTWAR /2). When supply PWR Factors State). (Figure 21). Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor or 3.3 V CMOS logic levels. Parity check is performed after transfer of each 16-bit SPI data word.The SPI interface can be driven without series resistors provided that voltage ...

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... SOA1 PWM3_s PWM2_s PWM1_s PWM0_s s SR0_s DELAY2_s DELAY1_s DELAY0_ tOCM_s OCH_s OCM_s OCL_s 0 Auto_period Auto_period Retry_unli retry_s 1_s 0_s mited_s CSNS1_en CSNS0_en OV_dis DD_FAIL_en 5.0 V and before DD DD_FAIL_EN Analog Integrated Circuit Device Data Freescale Semiconductor D0 SOA0 ...

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... Table 13. Value of bit A Required for Addressing 0 Register Banks Value A (D13 channel 0 (default channel 1 Analog Integrated Circuit Device Data Freescale Semiconductor SO Returned Data OD8 OD7 OD6 OD5 OD4 ...

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... The DC motor profile only has two and I ). _OCL , I _OCL1 _OCxy_z , _OCH _OCM when _OCL3 (Table 16). Current Sense Ratio 0 CRS0 (default) 1 CRS1 and t ), and also OCH_s OCM_s Table OCH1 Analog Integrated Circuit Device Data Freescale Semiconductor , _OCL2 ) _OCL _OCL2 17. or ...

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... Table 19. OCM Current Threshold Selection OCM_s (D1) OCM Current Threshold 0 I _OCM1_s 1 Bit D0 (OCL_s) and D8 (HOCR) set the value of the lowest over-current threshold, as shown in Table Analog Integrated Circuit Device Data Freescale Semiconductor or OCM1_L Table 20. OCL Current Threshold Selection HOCR (D8) and I as _OCH _OCL ...

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... Normal Mode • Bits OD8 : OD0 are the contents of the selected SO 111 — CALIBRATION REGISTER 0 (Table 11) puts the device in Internal Clock & Internal PWM (Clock_int_s (Table 12). These is low, except CSB Table 12 gives the functional Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Latched faults can only be delatched by the procedure described in Fault Delatching. Analog Integrated Circuit Device Data Freescale Semiconductor = 0000 (STATR) The FAULTR_s register is reset when it is read out, 0 provided that the failure cause has disappeared and latched faults had been delatched. ...

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... IN0 IN1 FSOB SCLK CSB RSTB SI SO 8.0 k2 CONF0 75 k CONF1 SYNC CSNS External Control Circuitry direct controls (pedals, handles, etc.) V PWR VPWR 100 nF 1.0 µF HS0 20XS4200 22 nF LOAD 0 HS1 LOAD 1 GND Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... I/O I/O MCU SCLK CSB I I/O A/D GND VPWR Figure 22. Two Channels in Parallel / Recommended External Current Sense Circuit Analog Integrated Circuit Device Data Freescale Semiconductor µ PWR VDD 100 k 100 nF CLOCK FSB IN0 IN1 FSOB SCLK CSB ...

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... SOLDERING INFORMATION The 20XS4200 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board. 20XS4200 50 PACKAGING SOLDERING INFORMATION The AN2467 provides guidelines for Printed Circuit Board design and assembly. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... For the most current package revision, visit below. Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGE DIMENSIONS www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 20XS4200 51 ...

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... PACKAGING PACKAGE DIMENSIONS 20XS4200 52 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 20XS4200 53 ...

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... PACKAGING PACKAGE DIMENSIONS 20XS4200 54 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 20XS4200 55 ...

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... PACKAGING PACKAGE DIMENSIONS 20XS4200 56 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A PACKAGING PACKAGE DIMENSIONS 20XS4200 57 ...

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... PACKAGING PACKAGE DIMENSIONS 20XS4200 58 FK SUFFIX 23-PIN PQFN 98ASA00428D ISSUE A Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... REVISION DATE DESCRIPTION OF CHANGES 5/2012 • Initial release 1.0 6/2012 • Updated values in 2.0 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY Table 3, Static Electrical Characteristics REVISION HISTORY PACKAGE DIMENSIONS 20XS4200 59 ...

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