MAX5980EVKIT# Maxim Integrated, MAX5980EVKIT# Datasheet
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MAX5980EVKIT#
Specifications of MAX5980EVKIT#
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MAX5980EVKIT# Summary of contents
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... EN EN AUTO MIDSPAN EN_CL5 _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. for Power-over-Ethernet IEEE 802.3at/af Compliant S ® 0.25I Current-Sensing Resistor 70W per Port for PSE Applications ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ABSOLUTE MAXIMUM RATINGS (Voltages referenced unless otherwise noted.) EE AGND ....................................................................-0.3V to +80V DGND, SVEE_ ......................................................-0.3V to +0.3V V ........................ -0.3V to the lower (V DD OUT_ ....................................................-0. ...
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Quad, IEEE 802.3at/af PSE Controller ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive when entering ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive ...
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Quad, IEEE 802.3at/af PSE Controller ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive when entering ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive ...
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Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 ...
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Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 ...
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Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet TOP VIEW GATE1 OUT1 SVEE1 EN_CL5 AUTO MIDSPAN *CONNECT TO V PIN NAME 3-Wire Serial Interface Input Clock Line. Referenced to DGND. Connect to DGND if the I 1 SCL not used. Serial ...
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Quad, IEEE 802.3at/af PSE Controller PIN NAME Analog Low-Side Supply Input. Bypass with an external 100V, 0.1FF ceramic capacitor between AGND and V Digital High-Side Supply Output. Bypass with an external RC network; see the V 12 ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SCL SDAIN SDAOUT SERIAL PORT INTERFACE (SPI) AUTO MIDSPAN REGISTER FILE EN_CL5 A3–A0 INT CENTRAL LOGIC UNIT (CLU) AGND ANALOG INTERNAL DGND BIAS AND REFERENCES SUPPLY AND SUPPLIES MONITORS ...
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Quad, IEEE 802.3at/af PSE Controller Detailed Description The MAX5980 is a quad PSE power controller designed for use in IEEE 802.3at/af-compliant PSE. This device provides PD discovery, classification, current limit, and load disconnect detections. The device supports both fully automatic ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Semiautomatic (Semi) Mode Enter semiautomatic mode by setting the port operating mode (R12h, Table 19) to [10]. When entering semi mode, the DET_EN_ and CLASS_EN_ bits retain their previous states. When the DET_EN_ ...
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Quad, IEEE 802.3at/af PSE Controller To prevent damage to non-PD devices, and to protect itself from an output short circuit, the device limits the current into OUT_ to less than 2mA (max) during PD detection. In midspan mode, after every ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 80ms 150ms t 0V -4V -9.1V -18V -54V OUT_ AGND Figure 1. Detection, Classification, and Port Power-Up Sequence 2-Event PD Classification If the result of the first classification event is ...
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Quad, IEEE 802.3at/af PSE Controller 80ms 150ms t DET(1) 0V -4V -9.1V -18V -54V OUT_ AGND Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence V exceeds V and decreases at a slower RSENSE_ CUT pace when ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SENSE_ EE CLASS 4 V SU_LIM 212.5mV CLASS 0 –3 V SU_LIM 106.25mV V TH_FB 35mV Figure 3. Foldback Current Characteristics Foldback Current During startup and normal operation, an internal ...
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Quad, IEEE 802.3at/af PSE Controller Undervoltage and Overvoltage Protection The device contains undervoltage and overvoltage pro- tection features, and the flag bits can be found in the Supply Event register (R0Ah and R0Bh, Table 12) and the Watchdog register (R42h, ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet SDA/SDAIN t LOW SCL t HIGH t HD, STA t R START CONDITION Figure 5. Serial Interface Timing Details Table 3. Programmable Device Address Settings Device Address (AD0) The ...
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Quad, IEEE 802.3at/af PSE Controller START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet The device has a 7-bit long slave address (Figure 9). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for ...
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Quad, IEEE 802.3at/af PSE Controller CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5980 S SLAVE ADDRESS R/W Figure 11. Write Format, Control, and Single Data Byte Written CONTROL BYTE STORED ON STOP CONDITION ACKNOWLEDGE FROM THE MAX5980 S ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Operation with Multiple Masters When the device operates on a 3-wire interface with mul- tiple masters, a master reading the device should use repeated starts between the write that sets the device’s address ...
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Quad, IEEE 802.3at/af PSE Controller Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME STATUS 0Ch Port 1 Status R — 0Dh Port 2 Status R — 0Eh Port 3 Status R — 0Fh Port 4 Status ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME MAXIM RESERVED 20h Reserved — — 21h Reserved — — 22h Reserved — — 23h Reserved — — 24h Reserved — ...
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Quad, IEEE 802.3at/af PSE Controller Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME Developer 43h ID/Revision R/W DEV_ID[2] Number High-Power 44h R/W — Enable 45h Reserved —- — 46h Port 1 GPMD R/W — 47h Port ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Register Map and Description The device contains a bank of volatile registers that store its settings and status. The device features an I compatible, 3-wire serial interface, allowing the registers to be fully ...
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Quad, IEEE 802.3at/af PSE Controller Interrupt Mask Register (R01h) The Interrupt Mask register (R01h, Table 7) contains mask bits that suppress the corresponding interrupt bits in register R00h (active-high). Setting mask bits low individually disables the corresponding interrupt signal. When ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Detect Event Register (R04h/R05h) The Detect Event register (R04h/R05h, Table 9) records detection/classification events for the port. On power-up or after a reset condition, the Detect Event register is set to a default ...
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Quad, IEEE 802.3at/af PSE Controller Startup Event Register (R08h/R09h) The Startup Event register (R08h/R09h, Table 11) records port startup failure events and current-limit disconnect timeout events. On power-up or after a reset condition, the Fault Event register is set to ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Status Registers (R0Ch–R11h) Port Status Registers (R0Ch–R0Fh) The Port Status registers (R0Ch–R0Fh, Table 13) record the results of the port detection and classification at the end of each phase in three encoded bits. ...
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Quad, IEEE 802.3at/af PSE Controller Power Status Register (R10h) The Power Status register (R10h, Table 16) records the current status of port power. On power-up or after a reset condition, the port is initially unpowered and the Power Status register ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Configuration Registers (R12h–R17h) Operating Mode Register (R12h) The Operating Mode register in the device (R12h, Table 19) contains 2 bits per port that set the port mode of operation. Table 20 details how ...
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Quad, IEEE 802.3at/af PSE Controller Detection and Classification Enable Register (R14h) The Detection and Classification Enable register (R14h, Table 22) is used to enable detection and classification routines for the ports power-up or after a reset con- dition, ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Miscellaneous Configuration 1 Register (R17h) The Miscellaneous Configuration 1 register (R17h, Table 24) is used for several functions that do not cleanly fit within one of the other configuration catego- ries ...
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Quad, IEEE 802.3at/af PSE Controller Pushbutton Registers (R18h–R1Ah) Detection/Classification Pushbutton Register (R18h) The Detection/Classification Pushbutton register (R18h, Table 25) is used as a pushbutton to set the corre- sponding bits in the Detection and Classification Enable register (R14h, Table 22). ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet General Registers (R1Bh–R1Fh) The ID register (R1Bh, Table 28) keeps track of the device ID number and revision. The device’s ID code is stored in ID_CODE[4:0] (R1Bh[7:3]) and is 11010. Contact the factory ...
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Quad, IEEE 802.3at/af PSE Controller TLIM Programming Registers (R1Eh and R1Fh) The TLIM Programming registers (R1Eh/R1Fh, Table 30) are used to adjust the t current-limit timeout duration. LIM On a power-up or after a reset condition, this register is set ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Current/Voltage Readout Registers Port Current Registers (R30h, R31h, R34h, R35h, R38h, R39h, and R3Ch, R3Dh) The Port Current registers (Tables 32 and 33) provide port current readout when a port is powered on. ...
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Quad, IEEE 802.3at/af PSE Controller Port Voltage Registers (R32h, R33h, R36h, R37h, R3Ah, R3Bh, R3Eh, and R3Fh) The Port Voltage registers (Tables 34 and 35) provide port voltage readout when a port is powered on power-up or after ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Other Functions Registers (R00h, R01h) Reserved Registers (R40h, R45h, R4Ah, R4Fh, R54h, R59h, R5Ah, R5Bh, R5Ch, R5Dh, R5Eh, R5Fh) These registers are at this time reserved. Writing to these registers will have no ...
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Quad, IEEE 802.3at/af PSE Controller High-Power Enable Register (R44h) The High-Power Enable register (R44h, Table 38) is used to enable the high-power features on the ports. On power-up or after a reset condition, if AUTO = 1, this register is ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Port Current-Limit Register (R48h, R4Dh, R52h, and R57h) The Port Current-Limit registers (Table 41) are used to set the current-limit SENSE_ voltage threshold for the corre- sponding port power-up or after ...
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Quad, IEEE 802.3at/af PSE Controller ___________Applications Information Layout Procedure Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimal performance: 1) Place the high-frequency input bypass capacitor (0.1FF ceramic capacitor from AGND ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 50I CURRENT SHARING 33nF WITH OTHER MAX5980 200I 3.3V 200I HPCL063L GND OPTIONAL BUFFER 200I HPCL063L OPTIONAL BUFFER SDA -54V 200I HPCL063L 3kI OPTIONAL BUFFER SCL -54V INTERNAL PULLUP TO V (AUTO MODE ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...