25LC320A-I/MS Microchip Technology, 25LC320A-I/MS Datasheet - Page 12
![IC EEPROM 32KBIT 10MHZ 8MSOP](/photos/6/59/65932/mfg_150_c04-111_ms_8-msop_sml.jpg)
25LC320A-I/MS
Manufacturer Part Number
25LC320A-I/MS
Description
IC EEPROM 32KBIT 10MHZ 8MSOP
Manufacturer
Microchip Technology
Datasheets
1.25AA320AT-IMNY.pdf
(30 pages)
2.25LC160A-ISN.pdf
(24 pages)
3.25AA320A-IP.pdf
(26 pages)
Specifications of 25LC320A-I/MS
Memory Size
32K (4K x 8)
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Organization
4 K x 8
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Access Time
50 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
25LCXXX
3.5
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 3-2:
The Write-In-Process (WIP) bit indicates whether the
25LCXXX is busy with a write operation. When set to a
‘
in progress. This bit is read-only.
FIGURE 3-6:
DS22131C-page 12
1
W/R = writable/readable. R = read-only.
WPEN
SCK
’, a write is in progress, when set to a ‘
W/R
CS
SO
7
SI
Read Status Register Instruction
(RDSR)
6
–
X
0
5
–
X
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
X
4
–
0
1
W/R
BP1
High-Impedance
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
0
4
R
1
’, no write is
1
5
WIP
R
0
Preliminary
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 3-3.
See Figure 3-6 for the RDSR timing sequence.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS Register
10
5
11
4
© 2009 Microchip Technology Inc.
12
3
13
2
14
1
15
0