25LC160C-I/P Microchip Technology, 25LC160C-I/P Datasheet - Page 10

• Manufacturer Part Number: 25LC160C-I/P
• Description: IC SRL EEPROM 2KX8 2.5V 8-PDIP
• Manufacturer: Microchip Technology

Specifications of 25LC160C-I/P

• Memory Size: 16K (2K x 8)
• Package / Case: 8-DIP (0.300", 7.62mm)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 3MHZ, 5MHZ, 10MHZ
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Organization: 2 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 100 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25XX160C/D
2.5
The Read Status Register (RDSR) instruction provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX160C/D is busy with a write operation. When set
to a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
DS22150A-page 10
W/R = writable/readable. R = read-only.
WPEN
SCK
W/R
CS
SO
7
1
SI
’, a write is in progress, when set to a ‘
Read Status Register (RDSR)
Instruction
6
–
X
0
5
–
X
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
X
4
–
0
1
W/R
BP1
High-Impedance
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
0
8
’, the latch prohibits writes to the array. The state of
1
’, the latch allows writes to the array, when set to a
6
9
Data from STATUS Register
10
5
11
4
© 2009 Microchip Technology Inc.
12
3
13
2
14
1
15
0