25AA080D-I/ST Microchip Technology, 25AA080D-I/ST Datasheet - Page 10
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25AA080D-I/ST
Manufacturer Part Number
25AA080D-I/ST
Description
IC SRL EEPROM 1KX8 1.8V 8-TSSOP
Manufacturer
Microchip Technology
Specifications of 25AA080D-I/ST
Memory Size
8K (1K x 8)
Package / Case
8-TSSOP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
3MHZ, 5MHZ, 10MHZ
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Organization
1 K x 8
Interface Type
SPI
Maximum Clock Frequency
10 MHz
Access Time
160 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
5 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
25XX080C/D
2.5
The Read Status Register (RDSR) instruction provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Write-In-Process (WIP) bit indicates whether the
25XX080C/D is busy with a write operation. When set
to a ‘
is in progress. This bit is read-only.
FIGURE 2-6:
DS22151A-page 10
W/R = writable/readable. R = read-only.
WPEN
SCK
W/R
CS
SO
7
1
SI
’, a write is in progress, when set to a ‘
Read Status Register (RDSR)
Instruction
6
–
X
0
5
–
X
0
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
STATUS REGISTER
X
4
–
0
1
W/R
BP1
High-Impedance
3
0
Instruction
2
W/R
BP0
0
2
3
0
WEL
4
R
1
0
’, no write
1
5
WIP
R
0
0
6
1
7
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read only. When set to
a ‘
register, when set to a ‘
the array or the STATUS register. The state of this bit
can always be updated via the WREN or WRDI com-
mands regardless of the state of write protection on the
STATUS register. These commands are shown in
Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is in Figure 2-7. These bits are nonvolatile and are
shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
7
8
1
’, the latch allows writes to the array or the STATUS
6
9
Data from STATUS Register
10
5
11
4
0
© 2009 Microchip Technology Inc.
12
3
’, the latch prohibits writes to
13
2
14
1
15
0