ISL94203IRTZ-T Intersil, ISL94203IRTZ-T Datasheet

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... ADDR FIGURE 1. TYPICAL APPLICATION DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. , Li-ion 2 P+ ...

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... Ordering Information PART NUMBER (Note 2) QUANTITY ISL94203IRTZ Bulk quantity ISL94203IRTZ-T7 (Note 1) 1000/reel ISL94203IRTZ-T (Note 1) 4000/reel ISL94203EVAL1Z NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

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Pin Descriptions PIN NUMBER SYMBOL VC8, VC7, Battery cell n voltage input. This pin is used to monitor the voltage of this battery cell. The voltage is level shifted to a ground 11, 13, 15, ...

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Pin Descriptions (Continued) PIN NUMBER SYMBOL 42 DFET Discharge FET Control. The ISL94203 controls the gate of a discharge FET through this pin. The power FET is an N-Channel device. The FET is turned on by the ISL94203 if all ...

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CS1 CURRENT SENSE GAIN AMPLIFIER x5/x50/x500 GAIN OVERCURRENT STATE MACHINE 30kΩ 220nF VBATT 1kΩ VC8 330kΩ 4.7nF 10kΩ CB8 20kΩ 1kΩ VC7 330kΩ 4.7nF 10kΩ CB7 20kΩ 1kΩ VC6 330kΩ 4.7nF 10kΩ CB6 20kΩ 1kΩ VC5 4.7nF 20kΩ 10kΩ CB5 ...

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Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Registers: Summary (EEPROM Registers: Summary (RAM Registers: Detailed (EEPROM Registers: Detailed (RAM Board Layout QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Circuit Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Simple Stand Alone Revision History About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7 ISL94203 FN7626.2 December 5, 2012 ...

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... Ld QFN (Notes 0.5V Continuous Package Power Dissipation .400mW BATT Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C Storage Temperature Range .-55°C to +125°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Operating Voltage 36V DD VCn-VC(n-1) Specified Range ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL V Supply Current Input Bias Current VCn Input Current CBn Input Current TEMPERATURE MONITOR SPECIFICATIONS External Temperature Accuracy Internal Temperature Monitor ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL CELL VOLTAGE MONITOR SPECIFICATIONS Cell Monitor Voltage Accuracy V Cell Monitor Voltage Accuracy V V Voltage Accuracy V BATT CURRENT SENSE AMPLIFIER SPECIFICATIONS Charge Current Threshold VCCTH Discharge ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS Discharge Overcurrent Detection V Threshold Discharge Overcurrent Detection Time t Short Circuit Detection Threshold V Short Circuit Current Detection Time Charge Overcurrent Detection V ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL VOLTAGE PROTECTION SPECIFICATIONS Overvoltage Lock-out Threshold V (Rising Edge - Any cell) [VCn-VC(n-1)] Overvoltage Lock-out Recovery V OVLOR Threshold - All cells Undervoltage Lock-out Threshold V (Falling Edge ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL End of Charge Threshold V (Rising Edge - Any cell) [VCn-VC(n-1)] End-of-Charge Threshold Hysteresis V Sleep Mode Timer Watchdog Timer t TEMPERATURE PROTECTION SPECIFICATIONS Internal Temperature Shutdown T ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL Cell Balance Max Voltage Delta V Threshold (Rising Edge - Any Cell) [VCn-VC(n-1)] Cell Balance Max Voltage Delta V CBDUH Threshold Hysteresis WAKE UP SPECIFICATIONS Device CHMON Pin ...

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Electrical Specifications V operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL SCL Clock Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the Bus Must Be Free Before Start ...

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Symbol Table WAVEFORM INPUTS MUST BE STEADY MA Y CHANGE FROM LOW TO HIGH MA Y CHANGE FROM HIGH TO LOW Timing Diagrams External Temperature Configuration TEMPO PIN xT1 PIN xT2 PIN THERMISTORS: 10k, MuRata XH103F Wake-up Timing LDMON PIN ...

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V WKUP1 CHMON PIN ~3s LDMON CHECK DFET/CFET RGO ~4ms COMMUNICATION Change in FET Control SCL BIT BIT SDA 3 2 DATA ~1µs or ~500µs IF BOTH FETS OFF DFET/CFET TURN ON FETSOFF PIN DFET/CFET TURN ON ...

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Automatic Temperature Scan MONITOR TIME = 120µs TEMPO PIN EXTERNAL TEMPERATURE xTn DELAY TIME = 20µs CBOT, DOT, COT BITs SEE FIGURE 3 FOR TEST CIRCUIT Serial Interface Timing Diagrams BUS TIMING SCL t SU:STA t HD:STA SDA (INPUT TIMING) ...

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Discharge Overcurrent/Short Circuit Monitor LDMON PIN DETECTS 2 LDMON PULSES ABOVE THRESHOLD OCD V DSENSE t SCD ‘0’ DOC BIT ‘0’ DSC BIT SD OUTPUT V +15V DD DFET OUTPUT Charge Overcurrent Monitor (Assumes NO_OCCR bit is ...

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Functional Description This IC is intended stand-alone battery pack monitor provides monitor and protection functions without using an external microcontroller. The part locates the power control FETs on the high side with a built-in charge ...

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Pack Configuration A register in EEPROM (CELLS) identifies the number of cells that are supposed to be present, so the ISL94203 only scans these cells. This register is also used for the cell balance operation. The register contents are a ...

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If the cell voltages do not read correctly, then the ISL94203 remains in the POR loop until conditions are valid for ...

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Wake-up Circuit When in a sleep mode, the wake up circuit detects that the output pin is pulled low (as might be the case when a load is attached to the pack and the FETs are off) or pulled high ...

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CELL VOLTAGE LESS THAN UVLO FOR 160ms AND UVLOPD = 1} OR RGO < 1.2V OR PDWN BIT SET TO “1” WAKE UP SIGNAL (EITHER CHARGER OR LOAD) ANY CELL VOLTAGE DROPS BELOW SLEEP THRESHOLD FOR SLEEP DELAY TIME ...

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VCn0 CELL n VC4 CELL 4 VC3 CELL 3 VC2 CELL 2 VC1 CELL 1 VC0 Open Wire Detection There is a special open battery wire detection function on this device. The most important reason for an open wire detection ...

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To increase the input filtering, the preferred method is to increase the size of the capacitors. PACK CELL IMBALANCE VC - MAX CBAL FETs TURN OFF VC MIN CELLF BIT 1s (NOTE 12) OPEN WIRE SCAN ~160ms (DEFAULT) ...

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Current and Voltage Monitoring There are two main automatic processes in the ISL94203. The first are the current monitor and overcurrent shutdown circuits. The second are the voltage, temperature and current analog to digital scan circuits. Current Monitor The current ...

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TABLE 2. MAXIMUM CURRENT MEASUREMENT RANGE GAIN VOLTAGE RANGE SETTING (mV) 5x -250 to 250 50x - 500x -2.5 to 2.5 The second part is the analog current direction, overcurrent and short circuit detect mechanisms. This circuit is ...

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If the µCFET bit is 1, then the external µC must control the power FETs. • A discharge short circuit condition exists when the voltage across the external sense resistor exceeds the discharge short circuit threshold, set by ...

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NORMAL OPERATION MODE SENSE CURRENT t OCCT CHARGER STILL CONNECTED V CHMON CHMON PIN CMON_EN (FROM µC) COC BIT (µCFET = “0”) COC BIT (µCFET = “1”) CFET NOTES: 14. When µCFET = “1”, COC bit is reset when the ...

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NORMAL OPERATION MODE BATTERY VOLTAGE V LDMON LDMON PIN LMON_EN (FROM µC) V DSC V OCD OCDT DFET NOTE 16 CFET NOTE 16 PCFET NOTE 16 DOC (STAND ALONE) DSC DOC (EXTERNAL CONTROL) LD_PRSNT FIGURE 22. DISCHARGE ...

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... See Figure 23 for details on the scan sequence. During manufacture, Intersil provides calibration values in the EEPROM for each cell voltage reading. When there is a new conversion for a particular voltage, the calibration is applied to the conversion ...

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Cell Voltage Monitoring The circuit that monitors the input cell voltage multiples the cell voltage by 3/8. The ADC converts this voltage to a digital value, using a 1.8V internal reference. The ADC produces a calibrated 14-bit value, but only ...

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During a scan, each cell is monitored for overvoltage, undervoltage, and sleep voltage. The voltage will also be converted to an ADC value and be stored in memory. If, during the scan, a voltage is outside the set limit, then ...

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V UVR LVCH UVLO t UV CHARGE? I PACK DISCHARGE SAMPLING FOR LOAD RELEASE (µCLMON PULSES) LMON_EN BIT (LOOKING FOR TOOL TRIGGER RELEASE) (FROM µC) LDMON PIN V LDMON CMON_EN BIT V WKUPC CHMON ...

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During the pulse period, a small current (~60 is output into the load. If there is µA) no load, then the LDMON voltage will be higher than the recovery threshold of 0.6V. When ...

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CHARGE SHUTDOWN DISCHARGE SHUTDOWN TURN OFF CFET TURN OFF DFET µCFET = 0 µCFET = 0 µCFET = 1 µCFET = 1 CHARGE OVER-TEMP DISCHARGE OVER-TEMP SET COT BIT SET DOT BIT xT2<DOTS or xT1<CBOTS xT1<DOTS xT2<COTS or xT1<COTS xT2>CUTS ...

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An exception to the above occurs if the xT2 sensor is configured as a FET temperature indicator (XT2M = “1”). In this case, the xT2 is not compared to the cell balance temperature thresholds used only for power ...

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REGISTER If HEXvalue is greater than or equal to 8191, then 10 ( HEXvalue 10 16384 – 14-bit value = --------------------------------------------------------------------------- - 8191 If HEXvalue is less than 8191, then 10 × HEXvalue 10 1.8 14-bit value = ------------------------------------------------- ...

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Note: This is also used in the cell voltage scan and open wire detect operation. • There are no limits to the number of cells that can be balanced at any one time, because ...

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CB OFF TIMER IS COUNTING CBOV BIT CBUV BIT CBOT BIT CBUT BIT OPEN BIT CELLF BIT SD PIN FETSOFF PIN 1 EOC CB_EOC CBDC BIT 2 CHING BIT CBDD 4 DCHING BIT When CASC = 1, the ISL94203 does ...

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1kΩ 22nF 10kΩ 316kΩ 39Ω 1kΩ 22nF 10kΩ 316kΩ 39Ω 1kΩ 22nF 10kΩ 316kΩ 39Ω 1kΩ 22nF 39Ω 10kΩ 316kΩ 1kΩ 22nF 39Ω 10kΩ 316kΩ 1kΩ 22nF 39Ω 10kΩ 316kΩ 1kΩ 22nF 39Ω 10kΩ 316kΩ 1kΩ 22nF 39Ω 10kΩ 316kΩ ...

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Power FET Drive The ISL94203 drives the power FETs gates with a voltage higher than the supply voltage by using external capacitors as part of a charge pump. The capacitors connect (as shown in Figure 2) and are nominally 4.7nF. ...

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CELLS VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS 5 CELLS VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS ...

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See: • “Page Write” on page 46 • “Register Protection” on page 49 The EEPROM contains an error detection and correction mechanism. When reading a value from the EEPROM, the device checks the data value for an error. If there ...

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SCL SDA START 2 FIGURE 34 START AND STOP BITS SCL FROM 1 MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START FIGURE 35. ACKNOWLEDGE RESPONSE FROM RECEIVER Write Operations BYTE WRITE For a byte write operation, ...

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WATCHDOG TIMER RESET SLAVE R BYTE T SDA BUS ISL94203: SLAVE BYTE = 50H (ADDR = 0) ISL94203: SLAVE BYTE = 52H (ADDR = 1) FIGURE ...

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WATCHDOG TIMER RESET SDA BUS WATCHDOG TIMER RESET Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. There are three ...

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EEPROM READ The ISL94203 has a special requirement when reading the EEPROM. An EEPROM read operation from the first byte of a four byte page (locations 0H, 4H, 8H, etc.) initiates a recall of the EEPROM page. This recall takes ...

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Registers: Summary (EEPROM) EEPROM (CONFIGURED AS 32 4-BYTE PAGES) PAGE ADDR Overvoltage Level 1 2 Overvoltage recovery Undervoltage Level 5 6 Undervoltage Recovery OVLO Threshold 9 A UVLO Threshold B 3 ...

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RAM PAGE ADDR 3 C CELLMAX Voltage D E ISense Voltage F Registers: Detailed (EEPROM) BIT ADDR Overvoltage Threshold 01 If any cell voltage is above this threshold voltage for an ...

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BIT ADDR End-of-Charge (EOC) Threshold 0D If any cell exceeds this level, then the EOC output and the EOC bit are set. Reserved 0E Low Voltage Charge Level 0F If the ...

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BIT ADDR Charge Overcurrent Time Out/Threshold 19 Time Out A charge overcurrent needs to remain for this time period prior to entering a charge overcurrent condition. This is an 12-bit value: ...

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BIT ADDR Cell Balance On Time (CBON) 25 Cell balance is on for this set amount of time, unless another condition indicates that there should be no cell balance. This is ...

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BIT ADDR Charge Over-Temperature Recovery Voltage 33 If external 1 temperature or the external 2 temperature rise above this setting, then the charge FET is turned on and the COT bit ...

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BIT ADDR Sleep Level Voltage 45 If any cell voltage is below this threshold voltage for a sleep delay time, the device goes into the sleep mode. Reserved 46 Sleep Delay ...

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TABLE 15. EEPROM REGISTER DETAIL (FEATURE CONTROLS) BIT/ ADDR CFPSD Reserved CELLF PSD 1 = Activates PSD output when a “Cell Fail” condition occurs Does NOT activate PSD output when a cell fails condition occurs. ...

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Registers: Detailed (RAM) BIT/ ADDR CUT COT (Read Charge under Charge only) temp over-temp These An external An external bits are thermistor thermistor set and shows the temp shows the temp reset by is lower than the ...

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TABLE 16. RAM REGISTER DETAIL (STATUS AND CONTROL) (Continued) BIT/ ADDR Analog MUX control bits (R/W) Voltage monitored by ADC when microcontroller overrides the internal scan operation. Current Gain Setting Current gain set when current is monitored ...

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TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) BIT ADDR Cell Minimum Voltage 8B This is the voltage of the cell with the minimum voltage. Reserved 8C Cell Maximum Voltage 8D This ...

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TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) (Continued) BIT ADDR Cell 7 Voltage 9D This is the voltage of CELL7. Reserved 9E Cell 8 Voltage 9F This is the voltage of ...

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TABLE 17. RAM REGISTER DETAIL (MONITORED VOLTAGES) (Continued) BIT ADDR 14-bit ADC Voltage AB This is the calibrated voltage out of the ISL94203 ADC. In normal scan mode, this value is ...

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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...

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Package Outline Drawing L48.6x6 48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 75 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 64 ISL94203 ...