ISL6730AFUZ Intersil, ISL6730AFUZ Datasheet - Page 14

• Manufacturer Part Number: ISL6730AFUZ
• Description: Power Factor Correction ICs PFC Controller
• Manufacturer: Intersil

Specifications of ISL6730AFUZ

• Rohs: yes
• Switching Frequency: 124 kHz
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: MSOP-10
• Minimum Operating Temperature: - 40 C

The MOSFET, SPP20N60C3 is selected.
P
The switching loss of the MOSFET consists of three parts: the
turn-on loss, the turn-off loss and the diode reverse recovery loss.
From the MOSFET datasheet, the typical switching losses curves
are provided.
When R
The switching loss due to transition is calculated:
P
P
The diode reverse recovery incurs additional power loss on the
MOSFET. This loss can be estimated as:
P
This loss is also related the di/dt during the MOSFET turn-on. The
di/dt can be found out from the MOSFET datasheet. At
R
Reverse Recovery Charge curve at T
Q
THE TOTAL LOSS ON THE MOSFET
P
OUTPUT CAPACITOR SELECTION
The output capacitor, C
300V during one line cycle. For capacitors with 20% tolerance,
the tolerance should be taken into consideration. Thus, the
output capacitance should be greater than:
Calculate the ripple RMS current through the capacitor:
Select the proper capacitor according to the hold time and ripple
RMS current requirement. The actual capacitance is 270µF.
It is important to make sure the output peak-to-peak ripple is
less than the minimum OVP threshold as specified in the
“Electrical Specifications” table on page 6. The ESR at 2 times of
the line frequency of the capacitor is found in the capacitor
datasheet. The ESR of the output capacitor is 770mΩ at 100Hz.
P
P
C
C
I
I
CORMS max
CORMS max
COND
SW
SW
RR
G
RR
COND
COND
RR
OUT
OUT
= 3.6Ω, the turn-on di/dt is 4000A/µs. From the Typical
= 220nC when I
=
=
=
=
≥
≥
Q
220nC 390V 62
(
(
+
G
--------------------------------------------- -
(
=
=
2 T
----------------------------------------------------
(
(
E
0.015mJ
2 20ms 300W
390
RR
P
= 3.6Ω, I
ON
⋅
V
⋅
I
3.3A
SW
2
DS max
2
OUT
•
HOLD
)
)
)
2
+
(
V
+
•
=
=
–
2
E
OUT
P
–
(
OFF
•
I
0.77A
⋅
300V
+
OUT max
RR
V
0.3Ω
⋅
)
D
0.007mJ
HOLD
P
2
•
•
= 6A, E
) F
F
OMAX
R
F
=
•
(
•
= 3.5A.
)
DS on
sw
OUT
2
3.27W
=
8 2
---------- -
sw
⋅
3π
(
kHz
(
3.27W
, is required to hold the output above
)
1
ISL6730A, ISL6730B, ISL6730C, ISL6730D
⋅
) 62kHz
ON
(
+
)
8 2
---------- -
•
•
1
3π
14
0.2
390V
------------- -
+
=
+
85V
= 0.015mJ, E
1.36W
0.2
5.32W
)
•
=
------------------------- -
V
J
)
–
RMSmin
232μF
V
= +125°C, the
1
=
OUT
+
=
1.36W
5.32W
1.633A
OFF
–
1
=
= 0.007mJ.
9.95W
(EQ. 28)
(EQ. 29)
(EQ. 30)
(EQ. 32)
(EQ. 33)
(EQ. 34)
(EQ. 35)
(EQ. 36)
(EQ. 27)
(EQ. 31)
(EQ. 37)
The minimum OVP threshold is 103% of the nominal output
value. The maximum output peak to peak ripple should be less
than 6% of the nominal value, which is 23.4V
CURRENT SENSING RESISTORS
Please refer to Equation 4 for calculation of the current sensing
resistor R
R
While a large R
R
available standard value resistors to determine the sense
resistor.
R
The maximum power dissipation on the R
and full load condition. The maximum power dissipation is
calculated:
P
P
The resistor, R
Equation 3, R
R
Where |x| stands for the ABS(x) function.
R
Select R
R
CURRENT LOOP COMPENSATION
The input current shaping is achieved by comparing the sensed
current signal to the sensed input voltage signal. The current
error amplifier (Gmi), together with the current compensation
network, adjusts the duty cycle so that the inductor current
traces the sensed rectified voltage. Thus, unity power factor is
achieved.
The compensation network consists of the Trans-Conductance
error amplifier (Gmi) and the impedance network (Z
goal of the compensation network is to provide a closed loop
transfer function with the sufficient 0dB crossing frequency
(f
difference between the open loop phase at f
following equations relate the compensation network’s poles,
zeros and gain to the components (R
V
V
0dB
CS
CS
CS
RCSMAX
RCSMAX
SEN
SEN
SEN
Opp
Opp
also incurs higher power dissipation. Select R
≥
) and adequate phase margin. Phase margin is the
=
is 3.16kΩ.
≥
≥
=
=
120mV 265V 0.92
------------------------------------------------------ -
0.068Ω
R
------------------------------------------------------------------- -
0.068Ω 6.6A 1.25
------------------------------------------------------- -
SEN
I
0.77A
OUT max
CS
CS
=
=
.
2 0.18mA
from available standard value resistors, the selected
2 300W
•
I
3.88A
SEN
(
⋅
INMAX
•
I
SEN
⋅
2 0.5 I
⋅
LPeak
CS
•
---------------------------------------------------------------------------------------------- -
•
(
should be greater than:
2π 100Hz 270μF 0.77Ω
renders better current sensing accuracy, larger
)
sets the overcurrent protection limit. From
2
⋅
(
2
------------------------------------------------------------------------------ -
•
⋅
•
⋅
2π 100Hz
(
•
OC
•
0.068Ω
(
2πf
R
1
⋅
(
CS
2πf
+
line
=
0.25
line
=
0.069Ω
⋅
⋅
=
3.117kΩ
C
)
) C
) 270μF 0.8
1.023W
OUT
⋅
⋅
OUT
ic
⋅
⋅
ESR
, C
⋅
⋅
ic
0.8
CS
)
and C
2
)
0dB
2
occurs at low line
+
P-P
+
1
1
.
and 180°. The
ip
CS
=
) in Figure 15.
February 26, 2013
ICOMP).
6.6V
from
FN8258.0
(EQ. 38)
(EQ. 39)
(EQ. 40)
(EQ. 41)
(EQ. 42)
(EQ. 43)
(EQ. 44)
(EQ. 45)
The