MSL2164-DUR Atmel, MSL2164-DUR Datasheet - Page 4

• Manufacturer Part Number: MSL2164-DUR
• Description: LED Lighting Drivers 16-String LED Driver Mult-PWM Modes 3FO
• Manufacturer: Atmel

Specifications of MSL2164-DUR

• Rohs: yes
• Operating Frequency: 20 MHz
• Maximum Supply Current: 350 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-64

Detailed Description
The MSL2164 and MSL2166 are highly integrated, flexible,
16-string LED drivers that use external MOSFETs to allow
high LED string currents and/or voltage. They include power
supply control to maximize efficiency and an advanced
PWM dimming control circuit for regional dimming and 3D
LED backlights. The drivers optionally connect to a video
subsystem to offer a simple architecture for use in LCD TV
backlight applications. Up to eight devices easily connect
together to drive large numbers of LED strings in a system.
The drivers provide multiple methods of controlling LED
brightness, through both LED regulation current control and
through PWM dimming. Set the LED current to control color
and use pulse width control for brightness management and
motion blur reduction. An on-chip EEPROM stores all the
default control register values, which are applied at start-up
and reconfigured through the serial data interface.
The MSL2164/MSL2166 interface to a microcontroller or
FPGA via SPI. The 20MHz bus addressable SPI interface
supports up to eight devices per Chip Select line. LED PWM
dimming is internally generated and synchronized to the
video VSYNC and HSYNC signals or directly controlled by an
external PWM drive signal applied to the PWM input. They
also feature phase spreading when external PWM dimming,
with a progressive 1/16 phase delay per string to reduce
LED power supply transient load and reduce power supply
input capacitor size.
PWM dimming is either synchronized to an external signal
applied to PHI, generated from the internal oscillator for
stand-alone applications or set directly by a signal at the
PWM input. For video systems, derive the PHI signal from
VSYNC. A 1x to 32x frequency multiplier processes PHI
for PWM dimming at multiples of the video frame rate.
Individually program each string’s “on” time with up to 12-bit
resolution when using the integrated PWM generator. The
final PWM dimming resolution depends upon the ratio of the
processed GSC to processed PHI frequencies, because the
“on” time is an integer number of GSC clock cycles between
0 and 4095, and is scaled by the value of the 12-bit global
intensity register. Phase delay is also an integer number of
processed GSC clock cycles, to synchronize timing to the
video frame. An on-chip frequency multiplier is provided in
order to fully utilize the 12-bit dimming range. The “on” time
count can be further scaled by a 12-bit global intensity value.
The processed GSC signal (the signal after being frequency
multiplied or divided, from either internally or externally
generated signal at GSC) precisely sets each string’s phase
delay so that it is synchronized to its physical position on
the LCD panel, relative to the beginning, middle or end
of the video frame. There are four different types of PWM
modulation modes, each defined by the part of the “on”
time or off-time set by the PHDLYn[11:0] register (part of the
STRnSET register). The modes are “forward,” “center,”
“reverse,” and “inverse”. All four modes use the PHDLYn
register to set the defined edge, and PWMn[11:0] to set
the “on” time as a number of processed GSC pulses. The
four different modes and register definitions are illustrated
in the figure below, showing the current waveforms. The
delay for string 0 is held at 0, and the PWM width is the
same for both strings and all the modes. Datan in the
figure refers to both the dimming data and the phase delay
data presented for the nth frame. For “forward” mode
PHDLYn specifies the number of processed GSC cycles
after the processed PHI edge that the string “on” time
begins and the PWMn register specifies the “on” time.
In this mode the falling edge varies with the “on” time
width programmed in the PWMn register, with the rising
edge held constant. In “center” mode, the delay is set
from the processed PHI edge to the center of the PWM on
pulse with width set by the PWMn register. Both the rising
and falling edge vary based on the PWMn with the center
held constant within a processed GSC cycle. In “reverse”
mode, the PHDLYn sets the delay from the next frame’s
processed PHI edge to the falling edge of the PWM “on”
time and the PWMn register determines the PWM “on”
time. Therefore the rising edge varies with PWMn and the
falling edge is held constant. In “inverse” mode, the delay
is set from the next frames PHI edge backwards to the
falling edge of the “on” time. The rising edge varies with
the PWMn register, while the falling edge is held constant.
STR0
PHI
STR0
STR1
STR1
STR0
STR1
STR0
STR1
Frame n-1
Data
n
PHDLY1
Frame n
Data
PWM1
n
n+1
n
PHDLY1
PHDLY1
PHDLY1
PWM1
PWM1
Frame n+1
n
Data
n+1
n
n
PWM1
n
PWM1
n+2
PWM1
PHDLY1
n
n+1
PHDLY1
PHDLY1
PHDLY1
n+1
PWM1
n
Frame n+2
PWM1
Data...
n+2
PWM1
n+1
n+1
n+1
n+1
PHDLY1
n+2
PWM1
PHDLY1
PHDLY1
PWM1
n+1
Frame n+3
n+2
Data...
PWM1
n+2
n+2
n+2
PHDLY1
n+2
n+2
“Reverse”
“Forward”
“Center”
“Inverse”