MAX6956ATL+TGH7 Maxim Integrated, MAX6956ATL+TGH7 Datasheet - Page 7
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MAX6956ATL+TGH7
Manufacturer Part Number
MAX6956ATL+TGH7
Description
LED Display Drivers 3-Wire-Interfaced 2.5V to 5.5V 20-Port and 28-Port GPIO and LED Driver
Manufacturer
Maxim Integrated
Datasheet
1.MAX6956ANI.pdf
(24 pages)
Specifications of MAX6956ATL+TGH7
Number Of Segments
28
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Supply Current
230 uA
Low Level Output Current
18 mA
Power Dissipation
762 mW
Figure 1. MAX6956 Functional Diagram
Shutdown mode is temporarily overridden by the dis-
play test function.
The MAX6956 operates as a slave that sends and
receives data through an I
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6956, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6956 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
_______________________________________________________________________________________________________
LED DRIVERS
28-Port LED Display Driver and I/O Expander
P4 TO P31
OR GPIO
AD0
AD1
SDA
SCL
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
D0
7-BIT DEVICE ADDRESS
SEGMENT OR
GPIO DATA
LED DRIVERS AND GPIO
SLAVE ADDRESS BYTE
MATCHER
ADDRESS
2
D1
C-compatible 2-wire inter-
8
7
Serial Interface
7
D2
Serial Addressing
CONFIGURATION
D3
DATA BYTE
INTENSITY
R/W
R/W
8
TEST
D4
D5
D6
TO/FROM DATA REGISTERS
D7
DATA BYTE
PORT CHANGE
DETECTOR
D8
is required on SDA. The MAX6956 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6956
7-bit slave address plus R/ W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
D9
D10
COMMAND BYTE
D11
REGISTER DECODE
D12
COMMAND
DATA
INTENSITY REGISTERS
COMMAND BYTE
TO COMMAND REGISTERS
PORT REGISTERS
8
TEST REGISTER
MASK REGISTER
CONFIGURATION
Start and Stop Conditions
D13
8
REGISTERS
CE
D14
R/W
D15
MAX6956
7