AT24C16B-TH-B Atmel, AT24C16B-TH-B Datasheet - Page 6

• Manufacturer Part Number: AT24C16B-TH-B
• Description: IC EEPROM 16KBIT 1MHZ 8TSSOP
• Manufacturer: Atmel

Specifications of AT24C16B-TH-B

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 16K (2K x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 256 K x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1.8 V, 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. Device Operation
6
AT24C16B
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see
page
below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see
ure 7-3 on page
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C16B features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal
operations.
2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be protocol reset by following these steps:
1. Create a start bit condition.
2. Clock 9 cycles.
3. Create another start bit followed by stop bit condition as shown below.
SCL
SDA
8). Data changes during SCL high periods will indicate a start or stop condition as defined
Start bit
8).
1
2
Dummy Clock Cycles
Figure 7-3 on page
3
8
8).
9
Start bit
5175E–SEEPR–3/09
Figure 7-2 on
Stop bit
Fig-