AT24HC04B-TH-B Atmel, AT24HC04B-TH-B Datasheet - Page 9

• Manufacturer Part Number: AT24HC04B-TH-B
• Description: IC EEPROM 4KBIT 1MHZ 8TSSOP
• Manufacturer: Atmel

Specifications of AT24HC04B-TH-B

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. Write Operations
Figure 5-2.
5227E–SEEPR–11/08
SDA LINE
Page Write
R
S
T
A
T
M
S
B
ADDRESS
DEVICE
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgement. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must
terminate the write sequence with a stop condition. At this time, the EEPROM enters an inter-
nally-timed write cycle, t
cycle, and the EEPROM will not respond until the write is complete, see
Figure 5-1.
PAGE WRITE: The 4K EEPROM is capable of a 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The
EEPROM will respond with a “0” after each data word received. The microcontroller must termi-
nate the page write sequence with a stop condition, see
The data word address lower four bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the fol-
lowing byte is placed at the beginning of the same page. If more than sixteen data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a “0” allowing the read or write sequence to continue.
S
B
L
W
W
R
R
T
E
I
/
SDA LINE
A
C
K
WORD ADDRESS (n)
Byte Write
R
S
T
A
T
M
S
B
WR
, to the nonvolatile memory. All inputs are disabled during this write
ADDRESS
DEVICE
C
A
K
DATA (n)
S
B
L
W
W
R
T
E
R
I
/
C
A
K
M
WORD ADDRESS
S
B
A
C
K
DATA (n + 1)
Figure
L
S
B
A
C
K
5-2.
DATA
C
A
K
Figure 5-1 on page
AT24HC04B
DATA (n + x)
C
A
K
S
O
P
T
A
C
K
9.
O
S
T
P
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