MAX7348AEP Maxim Integrated, MAX7348AEP Datasheet - Page 10

• Manufacturer Part Number: MAX7348AEP
• Description: Peripheral Drivers & Components - PCIs Low-EMI Key Switch & Sounder Controller
• Manufacturer: Maxim Integrated

The MAX7347/MAX7348/MAX7349 feature a 20ms mini-
mum bus timeout on the 2-wire serial interface, largely to
prevent the MAX7347/MAX7348/MAX7349 from holding
the SDA I/O low during a read transaction if the SCL
hangs for any reason before a serial transaction has
been completed. Bus timeout operates by causing the
MAX7347/MAX7348/MAX7349 to internally terminate a
serial transaction, either read or write, if the time between
adjacent edges on SCL exceeds 20ms. After a bus time-
out, the MAX7347/MAX7348/MAX7349 wait for a valid
START condition before responding to a consecutive
transmission. The bus timeout feature requires the serial
interface to operate above 50Hz bus speed. This feature
can be enabled or disabled under user control by writing
to the configuration register (Table 12).
A write to the MAX7347/MAX7348/MAX7349s’ key-scan
controller comprises the transmission of the
MAX7347/MAX7348/MAX7349s’ key-scan slave address
with the R/W bit set to zero, followed by at least 1 byte of
information. The first byte of information is the command
byte. The command byte determines which register of the
MAX7347/MAX7348/MAX7349 is to be written by the next
byte, if received. If a STOP condition is detected after the
command byte is received, then the MAX7347/MAX7348
/MAX7349 take no further action (Figure 7) beyond stor-
ing the command byte.
2-Wire Interfaced Low-EMI Key Switch
and Sounder Controllers
Figure 5. Acknowledge
Figure 6. Slave Address
10
______________________________________________________________________________________
TRANSMITTER
RECEIVER
Message Format for Writing the
SDA
SCL
SCL
SDA
SDA
BY
BY
CONDITION
START
MSB
S
0
Key-Scan Controller
1
Bus Timeout
1
1
1
2
A3
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX7347/MAX7348/MAX7349 selected by the
command byte (Figure 8).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7347/MAX7348/MAX7349 internal
registers (Table 7) because the command byte address
generally autoincrements (Table 4).
The MAX7347/MAX7348/MAX7349 are read using the
MAX7347/MAX7348/MAX7349s’ internally stored com-
mand byte as an address pointer, the same way the
stored command byte is used as an address pointer for
a write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
(Table 4). Thus, a read is initiated by first configuring
the MAX7347/MAX7348/MAX7349s’ command byte by
performing a write (Figure 7). The master can now read
n consecutive bytes from the MAX7347/MAX7348/
MAX7349, with the first data byte being read from the
register addressed by the initialized command byte.
When performing read-after-write verification, remem-
ber to reset the command byte’s address because the
stored command byte address is generally autoincre-
mented after the write (Figure 9, Table 4).
A2
Message Format for Reading the
LSB
A1
8
CLOCK PULSE FOR
ACKNOWLEDGE
R/W
Key-Scan Controller
ACK
9