MR4A16BYS35 Everspin Technologies, MR4A16BYS35 Datasheet
MR4A16BYS35
Specifications of MR4A16BYS35
Available stocks
Related parts for MR4A16BYS35
MR4A16BYS35 Summary of contents
Page 1
... AEC-Q100 Grade 1 (-40 to +125 °C) temperature range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2. ELECTRICAL SPECIFICATIONS................................................................. 3. TIMING SPECIFICATIONS.......................................................................... 4. ORDERING INFORMATION....................................................................... 5. MECHANICAL DRAWING.......................................................................... 6. REVISION HISTORY...................................................................................... How to Reach Us...................................................................................... .......... Copyright © Everspin Technologies 2012 MR4A16B RoHS MR4A16B Rev ...
Page 2
... Upper Byte Enable LB Lower Byte Enable DQ Data I/O V Power Supply DD V Ground Not Connect NC No Connection Copyright © Everspin Technologies 2012 Figure 1.1 Block Diagram UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE ROW COLUMN DECODER DECODER SENSE AMPS BIT MEMORY ARRAY ...
Page 3
... high low don’t care 1 Hi-Z = high impedance 2 Copyright © Everspin Technologies 2012 DQL0 A6 C DQL1 DQL2 DQL3 DD E A16 V DQL4 SS F A15 DQL5 ...
Page 4
... All voltages are referenced 0.5V. The AC value of V must not exceed applied V IN 20mA. Power dissipation capability depends on package characteristics and use environment. 3 Copyright © Everspin Technologies 2012 Table 2.1 Absolute Maximum Ratings Conditions Commercial Industrial AEC-Q100 Grade 1 ...
Page 5
... STARTUP READ/WRITE INHIBITED Copyright © Everspin Technologies 2012 Table 2.2 Operating Conditions Temp Range Commercial Industrial AEC-Q100 Grade 1 (min). See Power Up and Power Down Sequencing below. exceeds V DD DD, + 2.0 V (pulse width ≤ 10 ns) for I ≤ 20.0 mA (pulse width ≤ ...
Page 6
... CMOS standby current I (E ≥ 0.2 V and V SB2 max MHz) DD All active current measurements are measured with one address transition per cycle and at minimum cycle time. 1 Copyright © Everspin Technologies 2012 Table 2.3 DC Characteristics Conditions All All +100 μA OL ...
Page 7
... Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Output Copyright © Everspin Technologies 2012 Table 3.1 Capacitance Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and High Figure 3 ...
Page 8
... This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage (ADDRESS) Previous Data Valid Q (DATA OUT) Note: Device is continuously selected (E≤V A (ADDRESS) E (CHIP ENABLE) G (OUTPUT ENABLE) LB, UB (BYTE ENABLE) Q (DATA OUT) Copyright © Everspin Technologies 2012 Table 3.3 Read Cycle Timing Figure 3.3A Read Cycle 1 t ...
Page 9
... This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given 3 voltage or temperate, t (max) < t WLQZ A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) UB, LB (BYTE ENABLED) D (DATA IN) Q (DATA OUT) Copyright © Everspin Technologies 2012 Table 3.4 Write Cycle Timing 1 (W Controlled high) G low) G high) G low) ...
Page 10
... W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) UB, LB (BYTE ENABLE) D (DATA IN) Q (DATA OUT) Copyright © Everspin Technologies 2012 Table 3.5 Write Cycle Timing 2 (E Controlled Figure 3.5 Write Cycle Timing 2 (E Controlled) t AVAV ...
Page 11
... All write cycle timings are referenced from the last valid address to the first transition address. 2 Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled) A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) UB, LB (BYTE ENABLED) D (DATA IN) Q (DATA OUT) Copyright © Everspin Technologies 2012 2 t AVAV t AVEH t AVBL Hi -Z ...
Page 12
... Blank= Commercial (0 to +70 °C, C= Industrial (-40 to +85°C, M= AEC-Q100 Grade 1 (-40 to +125 °C) Revision Data Width 16 = 16-bit Type A = Asynchronous Density 4 =16Mb Magnetoresistive RAM Order Part Number MR4A16BMA35 1 MR4A16BMA35R MR4A16BYS35 MR4A16BYS35R MR4A16BCMA35 MR4A16BCMA35R MR4A16CBYS35 MR4A16BCYS35R MR4A16BMYS35 Preliminary MR4A16BMYS35R MR4A16B Rev. 8 8/2012 Preliminary ...
Page 13
... A 1.19 A1 0.22 b 0.31 D 10.00 BSC E 10.00 BSC D1 5.25 BSC E1 3.75 BSC DE 0.375 BSC SE 0.375 BSC e 0.75 BSC Ref Tolerance of, from and position aaa bbb ddd eee fff Copyright © Everspin Technologies 2012 Figure 5.1 48-FBGA PIN A1 INDEX SEATING PLANE ø 0.35mm Max 1.27 1.35 0.27 0.32 1. 0.36 0. ...
Page 14
... MECHANICAL DRAWING 0.71 REF. C SEATING PLANE Ref Min Nominal A A1 0.05 A2 0.95 b 0.30 c 0.12 D 22.10 E 11.56 E1 10.03 e 0.80 BSC L 0.40 L1 0.80 REF R1 0.12 R2 0.12 θ 0° θ1 0.40 θ2 θ3 Copyright © Everspin Technologies 2012 Figure 5.2 54-TSOP2 ⊕0.20(0.008 0.10 C Max 1.20 0.10 0.15 1.00 1.05 0.35 0.45 0.21 22.22 22.35 11.76 11.95 10.16 10.29 0.50 0. 0.25 - 8° 15° REF 15° REF 14 MR4A16B θ ...
Page 15
... All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical im- ...