DS2151QNB+ Maxim Integrated, DS2151QNB+ Datasheet - Page 30

• Manufacturer Part Number: DS2151QNB+
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2151QNB+

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 2.048 Mbps
• Supply Current (max): 65 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-44
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 5 V
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V
• Part # Aliases: 90-2151Q+NB0

7 FDL/FS EXTRACTION AND INSERTION
The DS2151Q can extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode
and from/into Fs bit position in the D4 framing mode. Since SLC-96 utilizes the Fs bit position, this
capability can also be used in SLC-96 applications. The operation of the receive and transmit sections
will be discussed separately.
7.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2ms (8 times 250µs). The
DS2151Q will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via
IMR2.4, the
has 2ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed
into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the
toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or
Fs pattern until an important event occurs.
The DS2151Q also contains a 0 destuffer that is controlled via the CCR2.0 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2151Q will
automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically
remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The
CCR2.0 bit should always be set to a 1 when the DS2151Q is extracting the FDL. More on how to use the
DS2151Q in FDL and SLC-96 applications is covered in a separate application note. Also, contact the
factory for C code software that implements both ANSI T1.403 and AT&T TR54016.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
RFDL7
(MSB)
SYMBOL
RFDL7
RFDL0
INT2
RFDL6
pin will toggle low indicating that the buffer has filled and needs to be read. The user
POSITION
RFDL5
RFDL.7
RFDL.0
RFDL4
NAME AND DESCRIPTION
MSB of the Received FDL Code
LSB of the Received FDL Code
30 of 60
RFDL3
RFDL2
RFDL1
INT2
pin will be
RFDL0
(LSB)