AT93C46E-PU Atmel, AT93C46E-PU Datasheet
AT93C46E-PU
Specifications of AT93C46E-PU
Related parts for AT93C46E-PU
AT93C46E-PU Summary of contents
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... The AT93C46E is available in space-saving 8- lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages. The AT93C46E is enabled through the Chip Select pin (CS) and accessed via a three- wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output DO pin ...
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... Table 2-2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: This parameter is characterized and is not 100% tested. AT93C46E 2 *NOTICE: Block Diagram MEMORY ARRAY DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR = 25° ...
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... CC 1.8V ≤ V ≤ 2.7V ≤ V ≤ 5. −0 0. 1.8V ≤ V ≤ 2. −100 µ AT93C46E = +1.8V to +5.5V, (unless otherwise noted) CC Min Typ Max 1.8 5.5 2.7 5.5 4.5 5.5 0.5 2.0 0.5 2.0 0.4 1.0 6.0 10.0 10.0 15.0 0.1 1 ...
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... This parameter is ensured by characterization. 3. Functional Description The AT93C46E is accessed via a simple and versatile three-wire serial communication inter- face. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location ...
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... Table 3-1. Instruction Set for the AT93C46E Instruction SB Op Code READ 1 10 EWEN 1 00 ERASE 1 11 WRITE 1 01 ERAL 1 00 WRAL 1 00 EWDS 1 00 READ (READ): The Read (READ) instruction contains the address code for the memory loca- tion to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “ ...
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... ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. AT93C46E 6 5207D–SEEPR–1/08 ...
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... Timing Diagrams Figure 4-1. Synchronous Data Timing Note: 1. This is the minimum SK period. Table 4-1. Figure 4-2. READ Timing High Impedance 5207D–SEEPR–1/08 μ s (1) Organization Key for Timing Diagrams I AT93C46E AT93C46E ...
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... Figure 4-3. EWEN Timing Note: 1. Requires a minimum of nine clock cycles. (1) Figure 4-4. EWDS Timing Note: 1. Requires a minimum of nine clock cycles. Figure 4-5. WRITE Timing HIGH IMPEDANCE DO AT93C46E 8 ... ... ... ... BUSY READY t WP 5207D–SEEPR–1/08 ...
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... Figure 4-7. ERASE Timing HIGH IMPEDANCE DO (1) Figure 4-8. ERAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC 5207D–SEEPR–1/ ... ... N-1 N AT93C46E ... D0 N BUSY STANDBY CHECK STATUS HIGH IMPEDANCE BUSY READY STANDBY CHECK STATUS BUSY HIGH IMPEDANCE READY t WP READY 9 ...
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... AT93C46E Ordering Information Ordering Code AT93C46E-PU (Bulk Form only) (1) AT93C46EN-SH-B (NiPdAu Lead Finish) (2) AT93C46EN-SH-T (NiPdAu Lead Finish) (1) AT93C46E-TH-B (NiPdAu Lead Finish) (2) AT93C46E-TH-T (NiPdAu Lead Finish) Notes: 1. “B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel. ...
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... Part marking scheme: AT93C46E 8-PDIP TOP MARK Seal Year |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) AT93C46E 8-SOIC TOP MARK |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 5207D–SEEPR–1/ SEAL YEAR | Seal Week 6: 2006 | | | 7: 2007 8: 2008 2009 Lot Number to Use ALL Characters in Marking BOTTOM MARK ...
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... AT93C46E 8-TSSOP TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * |---|---|---|---|---| |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| |---|---|---|---|---|---|---| |---|---|---|---|---|---|---| <- Pin 1 Indicator AT93C46E SEAL YEAR 6: 2006 7: 2007 W 8: 2008 9: 2009 SEAL WEEK 0: 2010 02 = Week 2 1: 2011 04 = Week 4 2: 2012 :: : :::: : 3: 2013 :: : :::: :: 50 = Week Week 52 5207D–SEEPR–1/08 ...
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... Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R 5207D–SEEPR–1/ TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) AT93C46E End View COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX SYMBOL A 0.210 A2 0.115 0.130 ...
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... JEDEC SOIC TOP VIEW TOP VIEW e e SIDE VIEW SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT93C46E TITLE 8S1, 8-lead (0.150" ...
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... Dimension D and determined at Datum Plane H. Package Drawing Contact: packagedrawings@atmel.com 5207D–SEEPR–1/ TITLE 8A2, 8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) AT93C46E L1 L End View COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL D 2.90 3 ...
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... Revision History Doc. Rev. 5207D 5207C 5207B 5207A AT93C46E 16 Date Comments 1/2008 Removed ‘preliminary’ status 11/2007 Modified ‘max’ value on AC Characteristics table 8/2007 Modified Part Marking Scheme Tables 1/2007 Initial document release 5207D–SEEPR–1/08 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...