LC72723MA-AH ON Semiconductor, LC72723MA-AH Datasheet - Page 6

• Manufacturer Part Number: LC72723MA-AH
• Description: Modulator / Demodulator
• Manufacturer: ON Semiconductor

RDCL/RDDA Output Timing
• Master mode
RST Operation
• Master mode
RDCL Control in Slave Mode
Notes:1. Start RDCL clock input after the READY signal goes low. Applications must stand by with RDCL held low when the READY pin is high.
RDCL setup time
RDCL high-level time
RDCL low-level time
Data output time
READY output time
Ready low-level time
2. Each time the RDCL input is switched from low to high to low, the application must check the READY signal level after the period t
3. When the above timing conditions are met, RDDA can be read at either the rise or fall of the RDCL signal.
4. After the last data from memory has been read, READY will be high once the period t
once RDCL has been set low. If READY is at the low level, the application may apply the next RDCL clock cycle. If READY is high, the application
must stop RDCL input at that point.
of data has been written to memory, READY will be low and the application will be able to read that data.
Parameter
Symbol
t
t
t
t
t
t
CS
CH
DC
RC
CL
RL
RDCL, RDDA
RDCL
RDCL
RDCL, RDDA
RDCL, READY
READY
LC72723, LC72723M
Conditions
RC
has elapsed after the fall of the RDCL signal. If even 1 bit
min
0.75
0.75
0
Caution: After an RST input, the
Ratings
typ
RDCL and RDDA outputs
stop at the high level until
the first RDS ID detection.
max
RC
0.75
0.75
107
has elapsed
No. 6037-6/8
Unit
ms
µs
µs
µs
µs
µs