EPCQ256SI16N Altera Corporation, EPCQ256SI16N Datasheet
EPCQ256SI16N
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EPCQ256SI16N Summary of contents
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www ...
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... Memory Array Organization EPCQ128 EPCQ256 16,777,216 bytes 33,554,432 bytes (128 Mb) (256 Mb) 256 512 4,096 8,192 65,536 131,072 End 1FFFFF 1FEFFF ... 1F2FFF 1F1FFF 1F0FFF 1EFFFF 1EEFFF ... 1E2FFF 1E1FFF 1E0FFF July 2012 Altera Corporation ...
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... Address Range for EPCQ32 Table 4 lists the address range for each sector in EPCQ32 devices. Table 4. Address Range for Sectors 63..0 and Subsectors 1023..0 in EPCQ32 Devices —Preliminary (Part Sector 63 62 July 2012 Altera Corporation Address Range (Byte Addresses in HEX) Subsector Start 31 1F000 30 1E000 ...
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... Memory Array Organization End 1FFFF 1EFFF ... 12FFF 11FFF 10FFF FFFF EFFF ... 2FFF 1FFF H’0000FFF End 7FFFFF 7FEFFF ... 7F2FFF 7F1FFF 7F0FFF 40FFFF 40EFFF ... 402FFF 401FFF 400FFF July 2012 Altera Corporation ...
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... Memory Array Organization Table 5. Address Range for Sectors 127..0 and Subsectors 2047..0 in EPCQ64 Devices —Preliminary (Part Sector July 2012 Altera Corporation Address Range (Byte Addresses in HEX) Subsector Start 1023 3FF000 1022 3FE000 ... ... 1010 3F2000 1009 3F1000 1008 ...
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... Memory Array Organization End FFFFFF FFEFFF ... FF2FFF FF1FFF FF0FFF FEFFFF FEEFFF ... FE2FFF FE1FFF FE0FFF 81FFFF 81EFFF ... 812FFF 811FFF 810FFF 80FFFF 80EFFF ... 802FFF 801FFF 800FFF 7FFFFF 7FEFFF ... 7F2FFF 7F1FFF 7F0FFF July 2012 Altera Corporation ...
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... Memory Array Organization Table 6. Address Range for Sectors 255..0 and Subsectors 4095..0 in EPCQ128 Devices —Preliminary (Part Sector July 2012 Altera Corporation Address Range (Byte Addresses in HEX) Subsector Start 1039 40F000 1038 40E000 ... ... 1026 402000 1025 401000 1024 ...
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... FF2000 4081 FF1000 4080 FF0000 Memory Array Organization End 1FFFFFF 1FFEFFF ... 1FF2FFF 1FF1FFF 1FF0FFF 1FEFFFF 1FEEFFF ... 1FE2FFF 1FE1FFF 1FE0FFF 101FFFF 101EFFF ... 1012FFF 1011FFF 1010FFF 100FFFF 100EFFF ... 1002FFF 1001FFF 1000FFF FFFFFF FFEFFF ... FF2FFF FF1FFF FF0FFF July 2012 Altera Corporation ...
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... Memory Array Organization Table 7. Address Range for Sectors 511..0 and Subsectors 8191..0 in EPCQ256 Devices —Preliminary (Part Sector 254 129 128 127 64 63 July 2012 Altera Corporation Address Range (Byte Addresses in HEX) Subsector Start 4079 FEF000 4078 FEE000 ... ... ...
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... F000 14 E000 ... ... 2 2000 1 1000 0 H’0000000 Memory Array Organization End 3EFFFF 3EEFFF ... 3E2FFF 3E1FFF 3E0FFF 1FFFF 1EFFF ... 12FFF 11FFF 10FFF FFFF EFFF ... 2FFF 1FFF H’0000FFF July 2012 Altera Corporation ...
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... If you are using the Quartus EPCQ256 device, you do not need to execute the 4BYTEADDREN operation. These software automatically enable the 4-byte addressing mode when programming the device. July 2012 Altera Corporation Table 8. The device must drive the nCS pin high after ...
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... Data Bytes DCLK f (MHz) MAX ( infinite 100 ( infinite 50 ( 100 ( infinite 100 ( infinite 100 ( infinite 100 0 100 0 100 1 100 ( 256 100 ( 256 100 ( 256 100 0 100 0 100 0 100 0 100 July 2012 Altera Corporation ...
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... Figure 3 shows the timing diagram for the write enable operation. Figure 3. Write Enable Operation Timing Diagram July 2012 Altera Corporation nCS ...
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... Extended quad input fast write bytes operation completion ■ Figure 4 shows the timing diagram for the write disable operation. Figure 4. Write Disable Operation Timing Diagram nCS DCLK DATA0 DATA Quad-Serial Configuration (EPCQ) Devices Datasheet Operation Code High Impedance Memory Operations 7 July 2012 Altera Corporation ...
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... The erase bulk operation is only available when all the block protect bits are set to 0. When any of the block protect bits are set to 1, the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation. July 2012 Altera Corporation Bit 7 TB BP2 ...
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... All sectors 1 All sectors Memory Operations Unprotected Area All sectors Sectors Sectors Sectors Sectors Sectors None None Unprotected Area All sectors Sectors Sectors Sectors Sectors Sectors None None July 2012 Altera Corporation ...
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... July 2012 Altera Corporation Memory Content BP0 Bit Protected Area 0 None 1 Upper 64 0 Upper 32 1 Upper 16 0 Upper 8 1 Upper 4 0 Upper half 1 All sectors Memory Content BP0 Bit Protected Area ...
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... None None None None Unprotected Area All sectors Sectors 1 to 127 Sectors 2 to 127 Sectors 4 to 127 Sectors 8 to 127 Sectors 16 to 127 Sectors 32 to 127 Sectors 64 to 127 None None None None None None None None July 2012 Altera Corporation ...
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... July 2012 Altera Corporation Memory Content BP0 Bit Protected Area None 0 Upper 256 1 Upper 128 0 Upper 64 1 Upper 32 0 Upper 16 1 Upper 8 0 Upper quarter 1 Upper half (sector 255) 0 All sectors ...
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... Unprotected Area All sectors Sectors 1 to 511 Sectors 2 to 511 Sectors 4 to 511 Sectors 8 to 511 Sectors 16 to 511 Sectors 32 to 511 Sectors 64 to 511 Sectors 128 to 511 Sectors 256 to 511 None None None None None None July 2012 Altera Corporation ...
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... Set the write in progress bit to 1 during the self-timed write status cycle and 0 when it is complete. July 2012 Altera Corporation Table 15 on page ...
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... Quad-Serial Configuration (EPCQ) Devices Datasheet 24-Bit Address ( MSB Memory Operations DATA Out 1 DATA Out MSB July 2012 Altera Corporation ...
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... If the fast read operation is shifted in while an erase, program, or write cycle is in progress, the operation is not executed and does not affect the erase, program, or write cycle in progress. July 2012 Altera Corporation Figure 9 shows the operation sequence of the fast read ...
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... Byte 2 Byte 3 Byte 4 Memory Operations Dummy Cycles July 2012 Altera Corporation ...
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... DATA1 Don’t Care DATA2 DATA3 ‘1’ Note to Figure 11: (1) To access the entire EPCQ256 memory, use 4-byte addressing mode. In the 4-byte addressing mode, the address width is 32-bit address. July 2012 Altera Corporation ...
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... Two Dummy Bytes MSB Memory Operations Silicon ID (Binary Value) b’0001 0101 b’0001 0110 b’0001 0111 b’0001 1000 b’0001 1001 Silicon MSB July 2012 Altera Corporation ...
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Write Bytes Operation This operation allows bytes to be written to the memory. You must execute the write enable operation before the write bytes operation. After the write bytes operation is completed, the write enable latch bit in the status ...
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... Data In 2 Data In 3 Data MSB MSB MSB Memory Operations Data In 256 MSB July 2012 Altera Corporation ...
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... DATA1 Don’t Care DATA2 DATA3 ‘1’ Note to Figure 15: (1) To access the entire EPCQ256 memory, use 4-byte addressing mode. In the 4-byte addressing mode, the address width is 32-bit address. July 2012 Altera Corporation ...
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... The write enable latch bit in the status register is reset to 0 before the erase cycle is complete. Quad-Serial Configuration (EPCQ) Devices Datasheet Operation Code 32. Memory Operations July 2012 Altera Corporation ...
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... The EPCQ device then goes into standby power mode. The I CC1 active and standby power modes. For more information, refer to July 2012 Altera Corporation Table 6 on page 6 and Table 7 on page 2 ...
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... DCLK high time CH t DCLK low time CL t Output disable time after read ODIS t Clock falling edge to DATA nCLK2D July 2012 Altera Corporation Parameter . WCLK t CL Bit N − 1 Parameter Quad-Serial Configuration (EPCQ) Devices Datasheet Page 33 Min Typical Max Unit — ...
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... USB-Blaster Download Cable User Guide ■ ■ EthernetBlaster II Communications Cable User Guide ■ EthernetBlaster Communications Cable User Guide Quad-Serial Configuration (EPCQ) Devices Datasheet Programming and Configuration File Support AN 370: Using the Serial FlashLoader with the July 2012 Altera Corporation ...
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... The I parameter refers to the high-level TTL or CMOS output current. OH (2) The I parameter refers to the low-level TTL or CMOS output current. OL July 2012 Altera Corporation Table 26 list information about the absolute maximum ratings, Parameter Condition Supply voltage With respect to GND DC input voltage ...
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... DATA2 4 5 GND Pin Information Condition Min Max Unit — — 100 — Condition Min Max Unit = 0 V — — 8 OUT Figure 22 and DCLK DATA0 V CC DATA3 DCLK DATA0 July 2012 Altera Corporation µ ...
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... You can leave these pins floating or you can connect them to V Figure 23 Pin-Out Diagram for EPCQ64, EPCQ128, and EPCQ256 Devices Note to Figure 23: (1) You can leave these pins floating or you can connect them to V July 2012 Altera Corporation DCLK CC ...
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... EPCQ device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. During read, configuration, or program operations, you can enable the EPCQ device by pulling the nCS signal low. July 2012 Altera Corporation ...
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... Pin Number Pin Number Pin Name in 8-Pin in 16-Pin SOIC SOIC Package Package — — DATA2 — — DATA3 1 7 nCS July 2012 Altera Corporation AS x4 Pin-Out Diagram Pin Number Pin Number Pin Type in 8-Pin in 16-Pin SOIC SOIC Package Package I/O 1 ...
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... EPCQ device on the rising edge of the DCLK signal. The data on the DATA pin changes after the falling edge of the DCLK signal and is latched in to the FPGA on the next falling edge of the DCLK signal. Connect the power pins to a 3.3-V power supply. Ground pin. July 2012 Altera Corporation ...
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... EPCQ devices. Table 28. EPCQ Device Ordering Codes Note to Table 28: (1) N indicates that the device is lead free. July 2012 Altera Corporation Device EPCQ16 EPCQ32 EPCQ64 EPCQ128 EPCQ256 Quad-Serial Configuration (EPCQ) Devices Datasheet Page 41 Serial Configuration (EPCS) (1) Ordering Code EPCQ16SI8N EPCQ32SI8N EPCQ64SI16N EPCQ128SI16N EPCQ256SI16N ...
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... Updated Figure 1, Figure 3, Figure 4, Figure 7, and Figure 13. ■ Updated Table 5, Table 11, Table 12, and Table 14. ■ Minor text edits. ■ Initial release. Document Revision History 12, Table 13, and Table 14 to include to include EPCQ16 and EPCQ32 section. 20, Table 27, and Table 28 to include July 2012 Altera Corporation ...