93LC46A/SN Microchip Technology, 93LC46A/SN Datasheet - Page 11

• Manufacturer Part Number: 93LC46A/SN
• Description: IC EEPROM 1KBIT 2MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 93LC46A/SN

• Memory Size: 1K (128 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: 0°C ~ 70°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 128 K x 8
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 1.5 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
FIGURE 2-10:
FIGURE 2-11:
 2010 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
CS
V
DI
DI
CC
must be 4.5V for proper operation of WRAL.
Write All (WRAL)
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1
1
High-Z
High-Z
WRAL TIMING FOR 93AA AND 93LC DEVICES
WRAL TIMING FOR 93C DEVICES
0
0
0
0
0
0
1
1
x
x
•••
•••
x
x
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
Dx
CC
Note:
must be 4.5V for proper operation of WRAL.
CSL
•••
•••
).
D0
D0
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
T
T
CSL
CSL
T
WL
T
WL
Busy
Busy
T
T
SV
SV
Ready
Ready
Busy
Busy
DS21749H-page 11
H
H
status from DO.
IGH
IGH
T
T
status of the
-Z
-Z
CZ
CZ