24AA00-I/SN Microchip Technology, 24AA00-I/SN Datasheet - Page 8

• Manufacturer Part Number: 24AA00-I/SN
• Description: IC EEPROM 128BIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24AA00-I/SN

• Memory Size: 128 (16 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 16 X 8
• Ic Interface Type: I2C
• Clock Frequency: 400kHz
• Supply Voltage Range: 1.7V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24AA00/24LC00/24C00
8.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
The 24XX00 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
device discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
device as part of a write operation.
FIGURE 8-1:
DS21178G-page 8
READ OPERATIONS
Current Address Read
Random Read
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
x = “don’t care” bit
S
T
A
R
T
S
1
0
1
Control
Byte
0 x x x 1
After the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. Then the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX00 will then issue an acknowledge and trans-
mits the eight bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the device discontinues transmission
(Figure 8-2). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the device transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24XX00 contains an
internal Address Pointer which is incremented by one
at the completion of each read operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
A
C
K
Sequential Read
Data
N
O
A
C
K
© 2007 Microchip Technology Inc.
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