24LC00-I/SN Microchip Technology, 24LC00-I/SN Datasheet - Page 5

• Manufacturer Part Number: 24LC00-I/SN
• Description: IC EEPROM 128BIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC00-I/SN

• Memory Size: 128 (16 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 16 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 24LC00-I/SNG; 24LC00-I/SNG

4.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
FIGURE 4-1:
FIGURE 4-2:
© 2007 Microchip Technology Inc.
SCL
SDA
Note:
SCL
SDA
(A)
Acknowledge
Condition
The 24XX00 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
Start
(B)
1
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE TIMING
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
2
3
Data from transmitter
4
Acknowledge
Address or
Valid
5
(C)
6
to Change
Allowed
7
24AA00/24LC00/24C00
Data
Acknowledge
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse.
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 4-2).
8
Bit
9
(D)
1
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
2
3
DS21178G-page 5
Condition
Stop
(C)
(A)
Of