MAX9178ETE Maxim Integrated, MAX9178ETE Datasheet - Page 10

• Manufacturer Part Number: MAX9178ETE
• Description: LVDS Interface IC
• Manufacturer: Maxim Integrated

Maintain the distance between the differential traces to
avoid discontinuities in differential impedance.
Minimize the number of vias to further prevent imped-
ance discontinuities.
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Balanced cables such as twisted pair offer superior
signal quality and tend to generate less EMI due to
canceling effects. Balanced cables tend to pick up
noise as common mode, which is rejected by the LVDS
receiver.
The MAX9178 is designed to protect the inputs (IN_,
EN, and EN) against latchup due to transient overshoot
and undershoot voltage. If the input voltage goes
above V
cuit limits input current to 1.5mA.
Quad LVDS Line Driver with High-ESD
Tolerance and Flow-Through Pinout
Figure 8. IEC 61000-4-2 Contact Discharge ESD Test Model
10
______________________________________________________________________________________
VOLTAGE
SOURCE
HIGH-
DC
CC
CHARGE-CURRENT-
or below GND by up to 1V, an internal cir-
LIMIT RESISTOR
50Ω TO 100Ω
R
C
150pF
C s
Overshoot and Undershoot
Cables and Connectors
STORAGE
CAPACITOR
RESISTANCE
DISCHARGE
330Ω
R
D
Voltage Protection
DEVICE
UNDER
TEST
The IEC 61000-4-2 standard specifies ESD tolerance
for electronic systems. The IEC 61000-4-2 model
(Figure 8) specifies a 150pF capacitor that is dis-
charged into the device through a 330Ω resistor. The
MAX9178 outputs are rated for IEC 61000-4-2 level 4
(±8kV Contact Discharge and ±15kV Air Discharge).
The Human Body Model (HBM, Figure 9) specifies a
100pF capacitor that is discharged into the device
through a 1.5kΩ resistor.
The IEC 61000-4-2 circuit discharges higher peak cur-
rent and more energy than the HBM circuit due to the
lower series resistance and larger capacitor.
A four-layer PC board that provides separate power,
ground, LVDS signals, and input signals is recom-
mended. Separate the LVTTL/LVCMOS and LVDS sig-
nals to prevent coupling.
Figure 9. Human Body ESD Test Model
VOLTAGE
SOURCE
HIGH-
DC
CHARGE-CURRENT-
LIMIT RESISTOR
1MΩ
R
C
100pF
C s
STORAGE
CAPACITOR
1.5kΩ
RESISTANCE
DISCHARGE
R
IEC 61000-4-2 Level 4
D
ESD Protection
Board Layout
DEVICE
UNDER
TEST