MAX9110EKA+ Maxim Integrated, MAX9110EKA+ Datasheet - Page 7

• Manufacturer Part Number: MAX9110EKA+
• Description: LVDS Interface IC 3.3V 500Mbps CMOS Rx/LVDS Tx
• Manufacturer: Maxim Integrated

Specifications of MAX9110EKA+

• Rohs: yes

Output trace characteristics affect the performance of
the MAX9110/MAX9112. Use controlled impedance
traces to match trace impedance to both transmission
medium impedance and termination resistor. Eliminate
reflections and ensure that noise couples as common
mode by running the differential traces close together.
Reduce skew by matching the electrical length of the
traces. Excessive skew can result in a degradation of
magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in impedance. Avoid 90° turns and
minimize the number of vias to further prevent imped-
ance discontinuities.
Transmission media should have a differential charac-
teristic impedance of about 100Ω. Use cables and con-
nectors that have matched impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon or
simple coaxial cable. Balanced cables, such as twisted
pair, offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Termination resistors should match the differential char-
acteristic impedance of the transmission line. Because
the MAX9110/MAX9112 are current-steering devices,
an output voltage will not be generated without a termi-
nation resistor. Output voltage levels are dependent
upon the termination resistor value. Resistance values
may range between 75Ω and 150Ω.
Minimize the distance between the termination resistor
and receiver inputs. Use a single 1% to 2% surface-
mount resistor across the receiver inputs.
_______________________________________________________________________________________
Cables and Connectors
Differential Traces
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
Termination
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input and LVDS sig-
nals from each other to prevent coupling. Separate the
input and LVDS signal planes with the power and ground
planes for best results.
MAX9110 TRANSISTOR COUNT: 765
MAX9112 TRANSISTOR COUNT: 765
PROCESS: CMOS
DIN_
MAX9110
MAX9112
+3.3V
DRIVER
0.001μF
Typical Operating Circuit
LVDS
0.1μF
R
T
= 100Ω
Chip Information
MAX9111
MAX9113
RECEIVER
+3.3V
Board Layout
0.001μF
OUT_
0.1μF
7