MC74AC138D ON Semiconductor, MC74AC138D Datasheet - Page 2

• Manufacturer Part Number: MC74AC138D
• Description: Encoders, Decoders, Multiplexers & Demultiplexers 2-6V 1-of-8 DeMux
• Manufacturer: ON Semiconductor

Specifications of MC74AC138D

• Product Category: Encoders, Decoders, Multiplexers & Demultiplexers
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: 74AC
• Number Of Lines (input / Output): 1 / 8
• Supply Voltage - Max: 6 V
• Supply Voltage - Min: 2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 1
• Number Of Output Lines: 8
• Factory Pack Quantity: 48

decoder/demultiplexer accepts three binary weighted inputs
(A
exclusive
MC74AC138/74ACT138 features three Enable inputs, two
active−LOW (E
outputs will be HIGH unless E
The
0
, A
1
, A
MC74AC138/74ACT138
2
FUNCTIONAL DESCRIPTION
) and, when enabled, provides eight mutually
active−LOW
TRUTH TABLE
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
1
E
H
X
X
, E
L
L
L
L
L
L
L
L
1
2
) and one active−HIGH (E
E
X
H
X
L
L
L
L
L
L
L
L
2
E
X
X
H
H
H
H
H
H
H
H
NOTE:
outputs
L
1
3
Inputs
and E
A
2
0
A
H
H
H
H
X
X
X
L
L
L
L
7
high−speed 1−of−8
0
2
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
are LOW and E
A
1
(O
A
H
H
H
H
0
X
X
X
L
L
L
L
6
1
0
−O
A
7
Figure 3. Logic Diagram
0
A
).
X
X
X
H
H
H
H
L
L
L
L
0
2
5
3
http://onsemi.com
). All
The
O
3
H
H
H
H
H
H
H
H
H
H
L
0
is
0
4
2
O
H
H
H
H
H
H
H
H
H
H
L
1
0
HIGH. This multiple enabled function allows easy parallel
expansion of the device to a 1−of−32 (5 lines to 32 lines)
decoder with just four MC74AC138/74ACT138 devices
and
MC74AC138/74ACT138 can be used as an 8−output
demultiplexer by using one of the active LOW Enable inputs
as the data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active−HIGH or active−LOW state.
E
3
1
O
E
H
H
H
H
H
H
H
H
H
H
L
2
2
E
3
0
one
2
O
Outputs
H
H
H
H
H
H
H
H
H
H
L
3
0
1
inverter
O
H
H
H
H
H
H
H
H
H
H
L
4
0
O
0
H
H
H
H
H
H
H
H
H
H
L
5
(See
O
H
H
H
H
H
H
H
H
H
H
L
6
O
H
H
H
H
H
H
H
H
H
H
L
Figure
7
4).
The