74LVC374AD NXP Semiconductors, 74LVC374AD Datasheet

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74LVC374AD

Manufacturer Part Number
74LVC374AD
Description
Flip Flops 3.3V OCTAL POS D-TYPE 3-S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC374AD

Product Category
Flip Flops
Rohs
yes
Number Of Circuits
1
Logic Family
LVC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
2.7 ns at 3.3 V
High Level Output Current
- 24 mA
Supply Voltage - Max
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-163
Minimum Operating Temperature
- 40 C
Number Of Input Lines
8
Number Of Output Lines
8
Factory Pack Quantity
38
Supply Voltage - Min
1.2 V
Part # Aliases
74LVC374AD,112

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1. General description
2. Features and benefits
The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW-to-HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVC374A is functionally identical to the 74LVC574A, but has a different pin
arrangement.
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 3 — 6 December 2012
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
CC
= 0 V
Product data sheet

Related parts for 74LVC374AD

74LVC374AD Summary of contents

Page 1

Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state Rev. 3 — 6 December 2012 1. General description The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. ...

Page 2

... Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC374AD 40 C to +125 C 74LVC374ADB 74LVC374APW 40 C to +125 C 74LVC374ABQ 40 C to +125 C 4. Functional diagram ...

Page 3

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state Fig 3. Functional diagram FF1 FF2 Fig 4. Logic diagram 74LVC374A Product data sheet FF1 D3 3-STATE OUTPUTS FF8 ...

Page 4

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 5. Pinning information 5.1 Pinning 374 GND 10 001aad040 Fig 5. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin 1 OE ...

Page 5

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 6. Functional description [1] Table 3. Function table Operating mode Input OE Load and read register L L Load register and disable H outputs H [ HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition ...

Page 6

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6 ...

Page 7

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage current I OFF-state output GND; O current I power-off OFF ...

Page 8

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t pulse width clock HIGH or LOW; see 3.6 V ...

Page 9

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 11. Waveforms CP input Qn output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times, and the ...

Page 10

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state CP input Dn input Qn output Measurement points are given in V and V are typical output voltage levels that occur with the output load The shaded areas indicate when the input is permitted to change for predicable output performance. ...

Page 11

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. ...

Page 12

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 ...

Page 13

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) ...

Page 16

... Revision history Document ID Release date 74LVC374A v.3 20121206 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74LVC374A v.2 20030514 74LVC374A v.1 ...

Page 17

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 18

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 19

... NXP Semiconductors Octal D-type flip-flop tolerant inputs/outputs; positive-edge trigger; 3-state 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics ...

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