74LVC16373ADG NXP Semiconductors, 74LVC16373ADG Datasheet - Page 9

• Manufacturer Part Number: 74LVC16373ADG
• Description: Latches 3.3V 16-BIT D TRANS LATCH 3-S
• Manufacturer: NXP Semiconductors

Specifications of 74LVC16373ADG

• Product Category: Latches
• Rohs: yes
• Number Of Circuits: 2
• Logic Type: TTL
• Logic Family: LVC
• Polarity: Non-Inverting
• Number Of Output Lines: 16
• High Level Output Current: - 24 mA
• Propagation Delay Time: 3 ns at 3.3 V
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TSSOP-48
• Mounting Style: SMD/SMT
• Number Of Input Lines: 16
• Factory Pack Quantity: 39
• Part # Aliases: 74LVC16373ADGG,512

NXP Semiconductors
Table 7.
Voltages are referenced to GND (ground = 0 V). For test circuit see
[1]
[2]
[3]
[4]
11. Waveforms
74LVC_LVCH16373A
Product data sheet
Symbol Parameter
t
t
C
h
sk(o)
Fig 6.
PD
Typical values are measured at T
t
t
t
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
C
P
f
C
V
N = number of inputs switching
(C
pd
en
dis
i
Qn output
Dn input
D
CC
PD
= input frequency in MHz; f
L
is the same as t
is the same as t
= output load capacitance in pF
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts
 V
hold time
output skew
time
power
dissipation
capacitance
Measurement points are given in
V
with the output load.
Input (Dn) to output (Qn) propagation delays
PD
GND
V
V
OL
Dynamic characteristics
CC
OH
OL
V
 V
I
2
and V
 f
CC
o
2
) = sum of the outputs
OH
 f
PLH
PZL
PLZ
i
are typical output voltage levels that occur
 N + (C
t
V
PHL
M
and t
and t
and t
Conditions
Dn to LE; see
V
per input; V
V
PZH
PHL
PHZ
M
CC
o
V
V
V
V
V
V
V
= output frequency in MHz
L
CC
CC
CC
CC
CC
CC
CC
.
.
.
= 3.0 V to 3.6 V
 V
amb
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
CC
= 25 C and V
2
…continued
 f
I
Table
16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
= GND to V
o
All information provided in this document is subject to legal disclaimers.
Figure 9
) where:
t
V
PLH
8.
M
Rev. 7 — 18 January 2013
CC
mgu772
74LVC16373A; 74LVCH16373A
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
D
in W).
Fig 7.
[3]
[4]
Figure
Qn output
LE input
T
GND
V
V
amb
+0.9
Min
OH
OL
2.5
2.0
0.9
V
Measurement points are given in
V
with the output load.
Latch enable input (LE) pulse width, and the
latch enable input to output (Qn) propagation
delays
-
-
-
-
I
OL
10.
= 40 C to +85 C 40 C to +125 C Unit
and V
Typ
1.0
10.8
13.0
15.0
V
t
OH
-
-
-
-
PHL
M
[1]
are typical output voltage levels that occur
t
W
V
M
Max
1.0
-
-
-
-
-
-
-
V
M
+0.9
Min
2.5
2.0
0.9
-
-
-
-
Table
V
t
© NXP B.V. 2013. All rights reserved.
PLH
M
8.
Max
V
1.5
M
-
-
-
-
-
-
-
mgu773
ns
ns
ns
ns
ns
pF
pF
pF
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