74LVC573ADB-T NXP Semiconductors, 74LVC573ADB-T Datasheet
74LVC573ADB-T
Specifications of 74LVC573ADB-T
Related parts for 74LVC573ADB-T
74LVC573ADB-T Summary of contents
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Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 5 — 19 February 2013 1. General description The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC573AD 40 C to +125 C 74LVC573ADB 74LVC573APW 40 C to +125 C 74LVC573ABQ 40 C to +125 C 40 C to +125 C 74LVC573ABX 4. Functional diagram ...
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... NXP Semiconductors Fig 3. Functional diagram LATCH LATCH Fig 4. Logic diagram 74LVC573A Product data sheet Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state LATCH ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 573 GND 10 001aad099 Fig 5. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin D[0: Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Operating modes Enable and read register (transparent mode) Latch and read register Latch register and disable outputs [ HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output GND; O current I power-off OFF CC leakage current I supply current I additional per input pin; V ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t disable time OE to Qn; see dis t pulse width LE HIGH; see W t set-up time nD to nCP; see su t hold time Dn to LE; see h t output skew time ...
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... NXP Semiconductors 11. AC waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 7. Input (Dn) to output (Qn) propagation delays LE input Qn output Measurement points are given in V and V are typical output voltage levels that occur with the output load. ...
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... NXP Semiconductors OE input Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 9. 3-state enable and disable times Dn input LE input Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance ...
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... NXP Semiconductors Test data is given in Table R = Load resistance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 11. Test circuit for measuring switching times Table 9. Test data Supply voltage Input ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 13 ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors Fig 16. Package outline SOT1045-2 (DHXQFN20) 74LVC573A Product data sheet Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 February 2013 74LVC573A © NXP B.V. 2013. All rights reserved ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations ...