CLC2011ISO8X Cadeka Microcircuits, CLC2011ISO8X Datasheet - Page 10

• Manufacturer Part Number: CLC2011ISO8X
• Description: Operational Amplifiers - Op Amps R-R I/O AMP 5.3V/us 4.9MHz 136uA
• Manufacturer: Cadeka Microcircuits

Specifications of CLC2011ISO8X

• Product Category: Operational Amplifiers - Op Amps
• Rohs: yes
• Number Of Channels: 2
• Common Mode Rejection Ratio (min): 81 dB
• Input Offset Voltage: 500 uV
• Input Bias Current (max): 90 nA
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Slew Rate: 5.3 V/us
• Shutdown: No
• Output Current: 16 mA
• Maximum Operating Temperature: + 85 C
• Gain Bandwidth Product: 2.5 MHz
• Minimum Operating Temperature: - 40 C
• Supply Current: 136 uA

Data Sheet
In order to determine P
needs to be subtracted from the total power delivered by
the supplies.
Supply power is calculated by the standard power
equation.
Power delivered to a purely resistive load is:
The effective load resistor (Rload
the effect of the feedback network. For instance,
Rload
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P
Quiescent power can be derived from the specified I
values along with known supply voltage, V
power can be calculated as above with the desired signal
amplitudes using:
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
Assuming the load is referenced in the middle of the
power rails or V
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the packages
available.
©2009-2010 CADEKA Microcircuits LLC
eff
P
D
DYNAMIC
in figure 3 would be calculated as:
can be found from
( I
P
LOAD
D
P
P
load
= P
supply
supply
(V
= (V
)
LOAD
RMS
Quiescent
= ((V
P
V
D
supply
/2.
S+
= V
R
= P
= ( V
L
)
D
RMS
- V
|| (R
, the power dissipated in the load
LOAD
supply
supply
= V
LOAD
+ P
LOAD
= V
)
f
RMS
S+
+ R
× I
Dynamic
)
- P
PEAK
)
RMS
RMS
- V
2
eff
RMS supply
)/Rload
g
load
)
) will need to include
S-
/ √2
× ( I
/ Rload
- P
eff
Load
LOAD
eff
Supply
)
RMS
. Load
S
Input Common Mode Voltage
The common mode input range extends to 250mV below
ground and to 250mV above Vs, in single supply operation.
Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition.
If the absolute maximum input voltage (700mV beyond
either rail) is exceeded, externally limit the input current to
±5mA as shown in Figure 5.
Driving Capacitive Loads
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency
response, and possible unstable behavior. Use a series
resistance, R
help improve stability and settling performance. Refer to
Figure 6.
1.5
0.5
Input
Figure 5. Circuit for Input Current Protection
2
1
0
-40
Figure 4. Maximum Power Derating
MSOP-8
10k
S
, between the amplifier and the load to
-20
SOT23-6
SOIC-8
Ambient Temperature (°C)
0
SOT23-5
20
40
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60
Output
80
10