FT221XQ-T FTDI, FT221XQ-T Datasheet - Page 36

• Manufacturer Part Number: FT221XQ-T
• Description: USB Interface IC USB to 8 bit SPI / FT1248 IC QFN-20
• Manufacturer: FTDI

Specifications of FT221XQ-T

• Rohs: yes
• Tradename: X-Chip

Configuration Memory Area (non-writable)
This is a reserved area and the application should not write to this area of memory. Any attempt to write
these locations will fail.
9.4 Hardware Requirements
The hardware is the same as for a typical USB-FT1248 application and no additional hardware or
programming voltages are required. The FT1248 connections are the same as shown in Section 5. For the
USB connections, either a bus-powered configuration (see Section 7.1 and 7.3) or a self-powered
configuration (see Section 7.2) could be used.
9.5 Protocol
The FT1248 MTP memory protocol consists of 3 commands:
For further details on the FT1248 protocol, refer to section 5.
9.5.1 Address MTP memory (0x05)
This consists of a command phase followed by 2 data bytes which represent the MTP memory address
allowing users to address, potentially, up to 64K byte addresses.
9.5.2 Write MTP memory (0x06)
This consists of a command phase followed by 1 data byte which shall be programmed into the MTP
memory at the address location set by the MTP memory address command.
9.5.3 Read MTP memory (0x07)
This consists of a command phase followed by 1 data byte which is the data read from the MTP memory
at the address location set by the MTP memory address command.
9.5.4 Examples of Writing and Reading
When performing MTP memory write and read requests via the FT1248 protocol, users must first issue
the MTP memory address command along with 2 bytes representing the MTP memory address. The
status and acknowledge phases of this command represents the current status of the MTP memory
(whether it is busy or not). If the MTP memory is being accessed during an FT1248 access then the
status and acknowledge of the respective command and data phases will NAK the master. The address
will only be updated when the MTP memory is inactive.
Writing
The first part of the communication sets the address, and this is followed by the write command along
with the data to be written. The MTP memory write itself will be initiated when the FT221X receives an
MTP memory write command followed by a single data byte. Two status phases occur during an MTP
write (once during the command phase and the other during the data phase). Both status phases
represent the current activity of the MTP memory (busy or not busy). A successful write will only occur
when both status phases acknowledge the master indicating that the MTP memory can start the write.
Users wishing to determine if the MTP memory write was successful should immediately try an EEPROM
read.
Reading
As with the writing process, the first part of the communication for a read sets the address. The read will
then be initiated when the FT1248 slave receives an MTP memory read command. The status during the
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Address MTP memory (0x05)
Write MTP memory (0x06)
Read MTP memory (0x07)
Copyright © 2013 Future Technology Devices International Limited
Document No.: FT_000630 Clearance No.: FTDI# 263
Version 1.2
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