MAX7448EUD+ Maxim Integrated, MAX7448EUD+ Datasheet - Page 6

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MAX7448EUD+

Manufacturer Part Number
MAX7448EUD+
Description
Active Filter Integrated Circuits (ICs)
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX7448EUD+

Number Of Channels
4
Cutoff Frequency
5 MHz
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP EP
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
96
When a sync pulse is detected on channel A, the DC
restore loop is activated for channel A, B, and C.
Channel D’s DC restore loop is activated by the sync
pulse on channel D. The function of the loop is to set
the DC level of the video signal to the specified level of
the signal type (R, G, B, CVBS). See Table 1 for clamp
levels and sync sources.
Use 0.1µF ceramic capacitors to AC-couple the inputs.
These input capacitors store a DC level so the outputs
are clamped to an appropriate DC voltage level.
The outputs are typically connected to a 75Ω series
back-match resistor followed by the video cable.
Because of the inherent divide-by-two of this configura-
tion, the voltage on the video cable is always less than
1V, complying with industry-standard video require-
ments such as the European SCART standard (which
allows up to 2V of DC on the video cable). The video
buffer can also drive an AC-coupled video load. Good
video performance is achieved with an output capacitor
as low as 220µF.
4-Channel RGB Video Filter with
Asynchronous CVBS Input
Table 1. Output Clamp Level and Sync
Source
6
_______________________________________________________________________________________
CHANNEL
A
B
C
D
Applications Information
CLAMP LEVEL
Output Considerations
(V)
0.9
1.5
1.5
0.9
Input Considerations
Output Clamp Level
SYNC SOURCE
Channel D
Channel A
Channel A
Channel A
The MAX7448 operates from a single +5V supply.
Bypass V
external components as close to the device as possible.
The TSSOP-EP package has an exposed pad on the
bottom of the package. This pad is electrically connect-
ed to GND and should be connected to the ground
plane for improved thermal conductivity. Do not route
signals under this package.
TRANSISTOR COUNT: 6300
PROCESS: BiCMOS
TOP VIEW
Power-Supply Bypassing and Layout
CC
DISABLE
to GND with a 0.1µF capacitor. Place all
GND
GND
INC
IND
INA
INB
1
2
3
4
5
6
7
MAX7448
TSSOP
Pin Configuration
Chip Information
14
13
12
11
10
9
8
Exposed Pads
OUTA
OUTB
OUTC
OUTD
V
GND
GND
CC

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