PCA9535ECDWR2G ON Semiconductor, PCA9535ECDWR2G Datasheet - Page 9

• Manufacturer Part Number: PCA9535ECDWR2G
• Description: Interface - I/O Expanders 16-BIT I/O EXPANDER
• Manufacturer: ON Semiconductor

Specifications of PCA9535ECDWR2G

• Rohs: yes
• Logic Family: PCA9535
• Number Of I/os: 16
• Maximum Operating Frequency: 400 KHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 55 C to + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-24
• Interface Type: I2C, SMBus
• Interrupt Output: Yes
• Operating Current: 1.65 V to 5.5 V
• Output Current: 50 mA
• Power Dissipation: 600 mW
• Product Type: I/O Expanders

Command Byte
by the command byte. The command byte determines which
of the following registers will be written or read.
Registers 0 and 1: Input Port Registers
logic levels of the pins, regardless of whether the pin is
defined as an input or an output by Registers 6 or 7. Writes
to these registers have no effect.
Registers 2 and 3: Output Port Registers
logic levels of the pins defined as outputs by Registers 6 and
7. Bit values in these registers have no effect on pins defined
Table 7. COMMAND BYTE
Table 8. INPUT PORT 0 REGISTER
Symbol
Default
Table 9. INPUT PORT 1 REGISTER
Symbol
Default
Table 10. OUTPUT PORT 0 REGISTER
Symbol
Default
Table 11. OUTPUT PORT 1 REGISTER
Symbol
Default
During a write transmission, the address byte is followed
These registers are input−only. They reflect the incoming
These registers are output−only. They reflect the outgoing
Bit
Bit
Bit
Bit
COMMAND
0
1
2
3
4
5
6
7
O0.7
O1.7
I0.7
I1.7
X
X
7
7
7
1
7
1
Input Port 0
Input Port 1
Output Port 0
Output Port 1
Polarity Inversion Port 0
Polarity Inversion Port 1
Configuration Port 0
Configuration Port 1
O0.6
O1.6
I0.6
I1.6
X
X
6
6
6
1
6
1
O0.5
O1.5
I0.5
I1.5
5
X
5
X
5
1
5
1
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REGISTERS
O0.4
O1.4
9
I0.4
I1.4
4
X
4
X
4
1
4
1
value ‘X’.
as inputs. In turn, reads from these registers reflect the values
that are in the flip−flops controlling the output selection, not
the actual pin values.
The externally−applied logic level determines the default
REGISTER
O0.3
O1.3
I0.3
I1.3
X
X
3
3
3
1
3
1
O0.2
O1.2
I0.2
I1.2
X
X
2
2
2
1
2
1
O0.1
O1.1
I0.1
I1.1
X
X
1
1
1
1
1
1
O0.0
O1.0
I0.0
I1.0
X
X
0
0
0
1
0
1