73S8010C-IMR/F2 Maxim Integrated, 73S8010C-IMR/F2 Datasheet - Page 12

• Manufacturer Part Number: 73S8010C-IMR/F2
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010C-IMR/F2

• Rohs: yes

7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs (most likely
resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is
initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and
generates an interrupt).
8 Activation Sequence
After Power on Reset, the INT signal is low until V
approximately 10 ms and the INT signal is high, the system controller may read the status register to see
if the card is present. If all the status bits are satisfactory, the system controller can initiate the activation
sequence by writing a ‘1’ to the Start/Stop bit (bit 0 of the Control register).
The following steps and
when the system controller initiates the Start/Stop bit (bit 0) of the control register:
1. Voltage V
2. Turn I/O to reception mode at the end of t
3. CLK is applied to the card at the end of t
4. RST (to the card) is set high at the end of t
12
t
t
t
Internal RC OSC
1
2
3
session is aborted.
= 0.510 ms (timing by 1.5 MHz internal Oscillator), I/O in reception mode
≥ 0.5 μs, CLK starts
 ≥ 42000 card clock cycles, RST set high
Start/Stop bit
PWRDN
PRES
CC
INT
to the card should be valid by the end of t
Figure 6
Figure 5: Power Down Mode Operation
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
show the activation sequence and the timing of the card control signals
Start/Stop = 1
Figure 6: Activation Sequence
~10ms
PWRDN during a card
session has no effect
2
.
1
.
3
.
OFF follows PRES regardless of PWRDN
DD
is stable. When V
1
. If V
CC
is not valid for any reason, then the
DD
has been stable for
EMV / ISO deactivation
time ~= 100 uS
PWRDN has effect when
the cardi s deactivated
Rev. 1.5