DS2483Q+U Maxim Integrated, DS2483Q+U Datasheet - Page 4

• Manufacturer Part Number: DS2483Q+U
• Description: I2C Interface IC SINGLE-CH 1-WIRE MASTER
• Manufacturer: Maxim Integrated

Specifications of DS2483Q+U

• Rohs: yes
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 1.71 V
• Maximum Operating Frequency: 400 kHz
• Maximum Operating Temperature: + 85 C
• Package / Case: TDFN-8
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Output Lines: 1
• Part # Aliases: 90-2483Q+00U

ELECTRICAL CHARACTERISTICS (continued)
(T
Note 1: Limits are 100% production tested at T
Note 2: The V
Note 3: The active pullup does not apply to the rising edge of a presence pulse outside of a
Note 4: Guaranteed design and not production tested.
Note 5: Except for t
Note 6: Although 1-Wire slave data sheets specify a t
Note 7: V
Note 8: I
Note 9: All I
Note 10: The DS2483 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if V
Note 11: The DS2483 provides a hold time of at least 300ns for the SDA signal (referenced to the V
Note 12: The maximum t
Note 13: A fast mode I
Note 14: C
Maxim Integrated
Input Current with Input Voltage
Between 0.1 O V
O V
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warmup Time
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
CC(MAX)
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
(wakeup from sleep mode) or after t
measure V
recovery after a short on the 1-Wire line.
t
from sleep mode.
bridge the undefined region of the falling edge of SCL.
must then be met. This requirement is met since the DS2483 does not stretch the low period of the SCL signal. Also the
acknowledge timing must meet this setup time (I
ing on the actual operating voltage and frequency of the application (I
W1L
2
PARAMETER
CCACT
B
C communication should not take place for the max t
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depend-
2
C timing values are referenced to V
and t
CI2C
CC(MAX)
refers to the V
RL
CI2C
voltage is applied at the SLPZ pin. V
F1
of the DS2483.
2
, all 1-Wire timing specifications are derived from the same timing circuit.
C bus device can be used in a standard mode I
.
HD:DAT
and 0.9
with Adjustable Timing and Sleep Mode
CC
must only be met if the device does not stretch the low period (t
level being applied in the application.
SYMBOL
t
t
OSCWUP
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:DAT
SU:STO
t
t
t
f
HIGH
LOW
SCL
BUF
C
C
I
I
B
I
OSCWUP
A
(Note 10)
(Note 4)
(Notes 11, 12)
(Note 13)
(Notes 4, 14)
(Notes 4, 8)
IH(MIN)
= +25°C and/or T
(power-on reset). The
W1L
Single-Channel 1-Wire Master
CI2C
and V
2
C bus specification Rev. 03, 19 June 2007).
and t
must always be < V
IL(MAX)
CONDITIONS
OSCWUP
RL
minimum of 1µs, 1-Wire slaves will accept the shorter 0.71µs
A
= +85°C. Limits over the operating temperature range and
levels.
2
C bus system, but the requirement t
or t
SWUP
Device Reset
2
C bus specification Rev. 03, 19 June 2007).
CC
time following a power-on reset or a wake-up
. The DS2483 measures V
CC
is switched off.
command does not cause the DS2483 to
1-Wire Reset
MIN
250
-10
0.6
1.3
0.6
0.6
0.6
1.3
LOW
0
IH(MIN)
) of the SCL signal.
TYP
of the SCL signal) to
command or during the
SU:DAT
CI2C
DS2483
MAX
+10
400
400
0.9
10
after t
2
R 250ns
SWUP
UNITS
kHz
FA
ms
pF
pF
Fs
Fs
Fs
Fs
Fs
ns
Fs
Fs
4