SST39LF512-45-4C-NH Microchip Technology, SST39LF512-45-4C-NH Datasheet
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SST39LF512-45-4C-NH
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SST39LF512-45-4C-NH Summary of contents
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... CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. ...
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... CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39LF512/010/020/040 and SST39VF512/010/020/040 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data# Polling ( When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ will produce the complement of the 7 true data. Once the Program operation is completed, DQ will produce true data ...
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... DQ0 DQ0 DQ0 FIGURE 2: Pin Assignments for 32-lead PLCC ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 X-Decoder I/O Buffers and Data Latches Control Logic SST39LF/VF512 SST39LF/VF512 ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A11 A11 A11 A11 A13 A13 A13 A13 A14 A14 A14 A14 A17 A17 NC NC WE# WE# WE# WE ...
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... Product Identification Software Mode 1. X can but no other value ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 TOP VIEW (balls facing down A11 NC1 OE# ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 TABLE 4: Software Command Sequence Command 1st Bus Sequence Write Cycle 1 Addr Data Byte-Program 5555H AAH Sector-Erase 5555H AAH Chip-Erase 5555H AAH 4,5 Software ID Entry 5555H AAH 6 Software ID Exit ...
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... A sector- or block-level rating would result in a END higher minimum specification. ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for DD 1 Limits Min Max Units ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters - V SST39VF512/010/020/040 Symbol Parameter T Read Cycle Time RC T Chip Enable Access Time CE T Address Access Time AA T Output Enable Access Time ...
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... Most significant address for SST39LF/VF512 for SST39LF/VF020 and A 17 FIGURE 7: WE# Controlled Program Cycle Timing Diagram ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 OLZ ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 5555 ADDRESS CPH OE# WE 7-0 SW0 Note Most significant address FIGURE 8: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 CE# OE# ...
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... Most significant address FIGURE 11: WE# Controlled Sector-Erase Timing Diagram ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 OEH T OE for SST39LF/VF512, A for SST39LF/VF010, 16 for SST39LF/VF020 and A ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 5555 2AAA ADDRESS A MS-0 CE 7-0 SW0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) ...
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... V (0 FIGURE 15: AC Input/Output Reference Waveforms TO DUT FIGURE 16: A Test Load Example ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 2AAA 5555 IDA T ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 FIGURE 17: Byte-Program Algorithm ©2010 Silicon Storage Technology, Inc. Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte ...
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... Erase Initiated Wait SCE Program/Erase Completed FIGURE 18: Wait Options ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Toggle Bit Byte-Program/ Erase Initiated Read byte Read same byte ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Software ID Entry Command Sequence Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 19: Software ID Command Flowcharts © ...
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... Address: 5555H Wait T SCE Chip erased to FFH FIGURE 20: Erase Command Sequence ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: 55H ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 PRODUCT ORDERING INFORMATION SST 39 LF 040 - XXXX - XXX ©2010 Silicon Storage Technology, Inc XXX X Environmental Attribute E Package Modifier leads balls balls (54 possible positions) Package Type B3 = TFBGA (0 ...
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... Data Sheet Valid combinations for SST39LF512 SST39LF512-45-4C-NHE SST39LF512-45-4C-WHE Valid combinations for SST39VF512 SST39VF512-70-4C-NHE SST39VF512-70-4C-WHE SST39VF512-70-4I-NHE SST39VF512-70-4I-WHE Valid combinations for SST39LF010 SST39LF010-45-4C-NHE SST39LF010-45-4C-WHE Valid combinations for SST39VF010 SST39VF010-70-4C-NHE SST39VF010-70-4C-WHE SST39VF010-70-4I-NHE SST39VF010-70-4I-WHE ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional Pin #1 .447 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. ...
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... Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. FIGURE 23: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 8.10 7.90 1.20 max ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 TOP VIEW 6.00 ± 0. CORNER DETAIL SEATING PLANE Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered. ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2010 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Description Write max for Erase operations in DD www ...