S25FL512SAGMFI013 Spansion, S25FL512SAGMFI013 Datasheet
S25FL512SAGMFI013
Specifications of S25FL512SAGMFI013
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S25FL512SAGMFI013 Summary of contents
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... CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL512S_00 ® ...
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... The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “ ...
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... Publication Number S25FL512S_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. ® ...
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Performance Summary Table 1.1 Maximum Read Rates with the Same Core and I/O Voltage (V Read Fast Read Dual Read Quad Read Table 1.2 Maximum Read Rates with Lower I/O Voltage (V Read Fast Read Dual Read Quad Read ...
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... FAC024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Software Interface 8. Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2 Flash Memory Array 8.3 ID-CFI Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.4 JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space 8.5 OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 June 13, 2012 S25FL512S_00_04 ...
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... Device ID and Common Flash Interface (ID-CFI) Address Map . . . . . . . . . . . . . . . . . . . . . 124 11.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 11.5 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Ordering Information 12. Ordering Information FL512S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13. Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 14. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 S25FL512S S25FL512S_00_04 June 13, 2012 ...
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Figures Figure 3.1 HOLD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 10.12 Write Registers (WRR 01h) Command Sequence – 16 data bits . . . . . . . . . . . . . . . . . . . . . 81 Figure 10.13 Write Enable (WREN 06h) ...
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Figure 10.59 Page Program (OTPP 42h) Command Sequence ...
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Tables Table 1.1 Maximum Read Rates with the Same Core and I/O Voltage (V Table 1.2 Maximum Read Rates with Lower I/O Voltage (V Table 1.3 Maximum Read Rates DDR (V Table 1.4 Typical Program and Erase Rates . . ...
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Table 11.7 Device Geometry Definition for 512-Mbit Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Overview 2.1 General Description The Spansion S25FL512S device is a flash non-volatile memory product using: MirrorBit technology - that stores two data bits in each memory array transistor Eclipse architecture - that dramatically improves program and erase performance process lithography This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SIngle I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands ...
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2.2 Migration Notes 2.2.1 Features Comparison The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P families. Parameter Technology Node Architecture Release Date Density Bus Width Supply Voltage Normal Read Speed ...
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... DDR read commands for SIO, DIO, and QIO. Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced Sector Protection feature found in several other Spansion parallel interface NOR memory families. 14 ...
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... Specification bulletins provide information on temporary differences in feature description or parametric variance since the publication of the last full data sheet. Contact your local sales office for details. Obtain the latest list of company locations and contact information at: http://www.spansion.com/About/Pages/Locations.aspx June 13, 2012 S25FL512S_00_04 ...
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... Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal ...
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3.2 Address and Data Configuration Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the SI signal. Data may be sent back to the host serially ...
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Serial Input (SI) / IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI ...
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The HOLD# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode. CS# SCK HOLD# SI_or_IO_(during_input) SO_or_IO_(internal) SO_or_IO_(external) 3.10 Core Voltage Supply ( ...
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... Do Not Use (DNU) A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal and may be left unconnected in the host system or may be tied to V signal routing channels ...
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Signal Protocols 4.1 SPI Clock Modes 4.1.1 Single Data Rate (SDR) The S25FL512S device can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes. Mode 0 with ...
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CPOL=0_CPHA=0_SCK CPOL=1_CPHA=1_SCK CS# Transfer_Phase SI SO 4.2 Command Protocol All communication between the host system and S25FL512S memory device is in the form of units called commands. All commands begin with an instruction that selects the type of information transfer ...
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... Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. All attempts to read the flash memory array during a program, erase write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation ...
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Command Sequence Examples CS# SCK SI SO Phase CS# SCK Phase CS# SCK SO Phase CS# SCK Instruction Phase CS# SCK Instruction Phase ...
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CS# SCK IO0 IO1 Phase CS# SCK IO0 IO1 IO2 IO3 Phase CS# SCK IO0 IO1 Instruction Phase CS# SCK IO0 IO1 IO2 IO3 Phase June 13, 2012 S25FL512S_00_04 S ...
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CS# SCK Phase CS# SCK IO0 7 6 IO1 Phase CS# SCK IO0 7 IO1 IO2 IO3 Phase Additional sequence diagrams, specific to each command, are provided in on page 70. 4.3 Interface States This ...
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Interface State Instruction Cycle Hold Cycle Single Input Cycle Host to Memory Transfer Single Latency (Dummy) Cycle Single Output Cycle Memory to Host Transfer Dual Input Cycle Host to Memory Transfer Dual Latency (Dummy) Cycle Dual ...
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Low Power Hardware Data Protection When V is less than V CC erase operations can not start when the core supply voltage is out of the operating range. 4.3.3 Power-On (Cold) Reset When the core voltage supply remains at ...
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... Dual Latency (Dummy) Cycle Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and HOLD# high ...
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... Quad Latency (Dummy) Cycle Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low. The host may drive the IO signals during these cycles or the host may leave the IO floating ...
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... DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high and CS# low ...
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Configuration Register Effects on the Interface The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the number of mode bit and latency cycles for each type of instruction. ...
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Electrical Specifications 5.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied (Note 1) IO Input voltage with respect to Ground (V Output Short Circuit Current Notes ...
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Input Signal Overshoot During DC conditions, input or I/O signals should remain equal to or between V transitions, inputs or I/Os may overshoot 2. 2. 5.3 Power-Up and Power-Down The device must ...
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Symbol V (min (cut-off (low (cut-off June 13, 2012 S25FL512S_00_04 ...
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DC Characteristics Applicable within operating ranges. Symbol V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH I Input Leakage Current LI Output Leakage I LO Current Active Power ...
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Timing Specifications 6.1 Key to Switching Waveforms Input Valid at logic high or low Symbol Output Valid at logic high or low Input Levels V + 0. ...
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AC characteristics tables assume clock and data signals have the same slew rate (slope). 4. DDR Operation. 6.2.1 Capacitance Characteristics OUT Note: 1. For more information on capacitance, please consult the IBIS models. 6.3 Reset 6.3.1 ...
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... The RESET# input provides a hardware method of resetting the flash memory device to standby state. RESET# must be high for t When RESET# is driven low for at least a minimum period of time (t operation in progress, tri-states all outputs, and ignores all read/write commands for the duration of t The device resets the interface to standby state ...
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SDR AC Characteristics Table 6.4 AC Characteristics (Single Die Package, V Symbol SCK Clock Frequency for READ and 4READ F SCK, R instructions SCK Clock Frequency for single commands as F SCK, C shown in SCK Clock Frequency for ...
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Table 6.5 AC Characteristics (Single Die Package, V Symbol F SCK Clock Frequency for READ, 4READ instructions SCK SCK Clock Frequency for all others SCK SCK Clock Period SCK ...
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Input / Output Timing CS# SCK SI SO CS# SCK SI SO CS# SCK ...
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SI_or_IO_(during_input) SO_or_IO_(during_output) CS# tWPS WP# SCK Phase June 13, 2012 S25FL512S_00_04 Figure 6.12 Hold Timing ...
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DDR AC Characteristics Symbol F SCK Clock Frequency for DDR READ instruction SCK SCK Clock Period for DDR READ instruction SCK Clock Rise Time (slew rate) crt t Clock Fall Time (slew rate) cft t ...
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6.5.1 DDR Input Timing CS# SCK SI_or_IO SO 6.5.2 DDR Output Timing CS# SCK SI SO_or_IO June 13, 2012 S25FL512S_00_04 ...
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SCK IO0 IO1 IO2 IO3 IO_valid Note: 1. Data Valid calculation at 66 MHz (min) – 6.75 ns – 1.5 ns – 600 ps – – ...
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7.1 SOIC 16-Lead Package 7.1.1 SOIC 16 Connection Diagram June 13, 2012 S25FL512S_00_04 Figure 7.1 16-Lead SOIC Package, ...
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SOIC 16 Physical Diagram S03016 — 16-Lead Wide Plastic Small Outline Package (300-mil Body Width S25FL512S ...
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7.2 FAB024 24-Ball BGA Package 7.2.1 Connection Diagram Note: Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use either package. June 13, 2012 S25FL512S_00_04 ...
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Physical diagram FAB024 — 24-ball Ball Grid Array ( mm) Package S25FL512S S25FL512S_00_04 June ...
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7.3 FAC024 24-Ball BGA Package 7.3.1 Connection Diagram Note: 1. Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use either package. June 13, 2012 S25FL512S_00_04 S h ...
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... BSC. SD/ SE 0.5/0.5 7.3.3 Special Handling Instructions for FBGA Packages Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time ...
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... The RDIDJ command (9Fh) reads information from a separate flash memory address space for device identification (ID) and Common Flash Interface (CFI) information. See Interface (ID-CFI) Address Map on page 124 The ID-CFI address space is programmed by Spansion and read-only for the host system. June 13, 2012 S25FL512S_00_04 ...
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... Figure 8.1, OTP Address Space on page 55 The OTP memory space is intended for increased system security. OTP values, such as the random number programmed by Spansion, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution. The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when set to 1 ...
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... Available for User Programming ... Available for User Programming 3E0 to 3FF Available for User Programming S25FL512S 16 Byte Random Number Byte 0 Contents Initial Delivery State (Hex) Number Spansion Programmed Random ... Number Number All bytes = FF ... All bytes = FF All bytes = FF All bytes = FF All bytes = FF All bytes = FF ...
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... The default state shown for each bit refers to the state after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit when the device is shipped from Spansion. Non-volatile bits have the same cycling (erase and program) endurance as the main flash array. ...
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... Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software- protected against program and erase commands. The BP bits are either volatile or non-volatile, depending on the state of the BP non-volatile bit (BPNV) in the configuration register. When one or more of the BP bits is set to 1, the relevant memory area is protected against program and erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to 0’ ...
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... Some read commands require additional latency cycles as the SCK frequency is increased. The following latency code tables provide different latency settings that are configured by Spansion. The High Performance versus the Enhanced High Performance settings are selected by the ordering part number. ...
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... Status Register are volatile or non-volatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to 000 when shipped from Spansion. When BPNV is set the BP2-0 bits in the Status Register are non- volatile. When BPNV is set the BP2-0 bits in the Status Register are volatile and will be reset to binary 111 after POR, hardware reset, or command reset ...
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Status Register 2 (SR2) Related Commands: Read Status Register 2 (RDSR2 07h). Bits Field Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU Erase Suspend (ES) SR2[1]: The Erase Suspend bit ...
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... Bank Register Write (BRWR 17h). The Bank Address register supplies additional high order bits of the main flash array byte boundary address for legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits of address (above A23) for all 3-byte address commands when EXTADD=0 ...
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ASP Register (ASPR) Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh). The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP) features. Bits Field Name 15 ...
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... The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data Learning Register (VDLR). When shipped from Spansion, the NVDLR value is 00h. Once programmed, the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR ...
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... Spansion Programmed Random Number Spansion standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number concatenated with the day and time of tester insertion. ...
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... The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT bit can be used to protect an address range of the main flash array from program and erase operations. The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register ...
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... PPB =”0” or its DYB = “0” Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it. When either bit is 0, the sector is protected from program and erase operations. The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection ...
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... Persistent Protection Bits The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related to each sector. When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time ...
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PPB Lock Bit (PPBL[0]) The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared locks all PPBs and when set allows the PPBs to be changed. The PLBWR ...
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... The password is all 1’s when shipped from Spansion located in its own memory space and is accessible through the use of the Password Program and Password Read commands. All 64-bit password combinations are valid as a password. The Password Mode, once programmed, prevents reading the 64-bit password and further password programming ...
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... Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. All attempts to read the flash memory array during a program, erase write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation ...
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each command rather than the signal timing and relationships. Following are some general signal relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of commands, see ...
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For backward compatibility to the 3-byte address instructions, the standard instructions can be used in conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to 0 (following power up and hardware reset), ...
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... Command Description Read Electronic Manufacturer Signature Read ID (JEDEC Manufacturer ID and JEDEC CFI) Read Electronic Signature Read Serial Flash Discoverable Parameters Read Status Register-1 Read Status Register-2 Read Configuration Register-1 Write Register (Status-1, Configuration-1) Write Disable Write Enable Clear Status Register-1 - Erase/Prog ...
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... Table 10.2 S25FL512S Command Set (sorted by function) (Sheet Command Function Name Erase Flash Array ERSP ERRS OTPP One Time Program Array OTPR DYBRD DYBWR PPBRD PPBP PPBE ASPRD Advanced Sector Protection ASPP PLBRD PLBWR PASSRD PASSP PASSU RESET Reset Reserved for ...
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... There are commands to read and program a separate One TIme Programmable (OTP) array for permanent data such as a serial number. There are commands to control a contiguous group (block) of flash memory array sectors that are protected from program and erase operations. There are commands to control which individual flash memory array sectors are protected from program and erase operations ...
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Reset There is a command to reset to the default conditions present after power on to the device. There is a command to reset (exit from) the Enhanced Performance Read Modes. 10.1.9 Reserved Some instructions are reserved for future ...
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... Common Flash Interface (CFI) information. The manufacturer identification is assigned by JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are assigned by Spansion. The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a vendor-specified software flash management program (driver used for entire families of flash devices. ...
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... SO Phase 10.2.4 Read Serial Flash Discoverable Parameters (RSFDP 5Ah) The command is initiated by shifting on SI the instruction code “5Ah”, followed by a 24-bit address of 000000h, followed by eight dummy cycles. The SFDP bytes are then shifted out on SO starting at the falling edge of SCK after the eight dummy cycles. The SFDP bytes are always shifted out with the MSB first. If the 24-bit address is set to any other value, the selected location in the SFDP space is the starting point of the data read ...
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Figure 10.5 Read Status Register-1 (RDSR1 05h) Command Sequence CS# SCK SI SO Phase 10.3.2 Read Status Register-2 (RDSR2 07h): The Read Status Register (RDSR2) command allows the Status Register-2 contents to be read from SO. ...
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... BAR[7]. BAR provides the high order addresses needed by devices having more than 128 Mbits (16 Mbytes), when using 3-byte address commands without extended addressing enabled (BAR[7] EXTADD = 0). Because this command is part of the addressing method and is not changing data in the flash memory, this command does not require the WREN command to precede it. ...
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CS# SCK SI SO Phase 10.3.7 Write Registers (WRR 01h): The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and Configuration Register. Before the Write Registers (WRR) command can ...
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The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits to define the size of the area that treated as read-only. The Write Registers (WRR) command ...
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... Notes: 1. The Status Register originally shows 00h when the device is first shipped from Spansion to the customer. 2. Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP# becomes IO2; therefore, it cannot be utilized. The WRR command has an alternate function of loading the Bank Address Register if the command immediately follows a BRAC command ...
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CS# SCK SI SO Phase 10.3.10 Clear Status Register (CLSR 30h): The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag not necessary to set the WEL bit before the Clear ...
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An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature. The AutoBoot register bits are non-volatile and provide: The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size ...
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CS# SCK SI SO Phase 10.3.13 AutoBoot Register Write (ABWR 15h) Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the ...
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Figure 10.20 Program NVDLR (PNVDLR 43h) Command Sequence CS# SCK Phase June 13, 2012 S25FL512S_00_04 ...
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Write VDLR (WVDLR 4Ah) Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, ...
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... 10.4 Read Memory Array Commands Read commands for the main flash array provide many options for prior generation SPI compatibility or enhanced performance SPI: Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR). ...
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Read (Read 03h or 4READ 13h): The instruction 03h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 03h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 13h is followed by a 4-byte address (A31-A0) ...
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10.4.2 Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch): The instruction 0Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 0Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 0Ch is followed ...
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The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address in sequential order after each byte of data is shifted out. The entire memory can therefore be read ...
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Then the memory contents, at the address given, is shifted out four bits at a time through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK ...
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For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and SO before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the ...
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Figure 10.31 Dual I/O Read Command Sequence (3-byte Address, BBh [ExtAdd=0], HPLC=00b) CS# SCK IO0 IO1 Phase Figure 10.32 Dual I/O Read Command Sequence (4-byte Address, BBh [ExtAdd=1], HPLC=10b) CS# SCK IO0 IO1 Phase Figure 10.33 ...
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EBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or ECh is followed by a 4-byte address (A31-A0) The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3 similar to the Quad Output ...
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Figure 10.35 Quad I/O Read Command Sequence (3-byte Address, EBh [ExtAdd=0], LC=00b) CS# SCK IO0 IO1 IO2 IO3 Phase Figure 10.36 Continuous Quad I/O Read Command Sequence (3-byte Address), LC=00b CS# SCK IO0 ...
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Figure 10.38 Continuous Quad I/O Read Command Sequence (4-byte Address), LC=00b CS# SCK IO0 4 0 IO1 5 1 IO2 6 2 IO3 7 3 Phase DN-1 10.4.7 DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh) The instruction 0Dh (ExtAdd=0) ...
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command sequence. The following sequences will release the device from this continuous DDR Fast Read mode; after which, the device can accept standard SPI commands: 1. During the DDR Fast Read Command Sequence, if the Mode ...
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Figure 10.41 DDR Fast Read Initial Access (4-byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b) CS# SCK Phase Note: 1. Example DLP of 34h (or 00110100). Figure 10.42 Continuous DDR Fast Read Subsequent Access CS# SCK S ...
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SCK (refer to Table 8.6, Latency Codes for DDR High Performance on page 58 Codes for DDR Enhanced High Performance on page in the Configuration Register (CR1). The HPLC table does not provide cycles for ...
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See Registers on page 63 (4-byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b) CS# SCK IO0 7 6 IO1 Phase Figure 10.45 Continuous DDR Dual I/O Read Subsequent Access (4-byte Address, ...
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value on IO0-IO3 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must ...
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Figure 10.47 DDR Quad I/O Read Initial Access (3-byte Address, EDh [ExtAdd=0], HPLC=11b) CS# SCK IO0 7 6 IO1 IO2 IO3 Phase Figure 10.48 Continuous DDR Quad I/O Read Subsequent Access (3-byte Address,HPLC=11b) CS# SCK IO0 IO1 ...
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... The programming process is managed by the flash memory device internal control logic. After a programming command is issued, the programming operation status can be checked using the Read Status Register-1 command ...
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Figure 10.51 Page Program (PP 02h or 4PP 12h) Command Sequence CS# SCK Phase Instruction 10.5.3 Quad Page Program (QPP 32h or 38h, or 4QPP 34h) The Quad-input Page ...
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10.5.4 Program Suspend (PGSP 85h) and Resume (PGRS 8Ah) The Program Suspend command allows the system to interrupt a programming operation and then read from any other non-erase-suspended sector or non-program-suspended-page. Program Suspend is valid only ...
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... Bulk Erase (BE 60h or C7h): The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations ...
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CS# SCK SI SO Phase 10.6.3 Erase Suspend and Resume Commands (ERSP 75h or ERRS 7Ah) The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or program data ...
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Figure 10.57 Erase Suspend (ERSP 75h) Command Sequence CS# SCK Phase Suspend Instruction Phase CS# SCK SI SO Phase Table 10.6 Commands Allowed During Program or Erase Suspend ...
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Table 10.6 Commands Allowed During Program or Erase Suspend (Sheet Instruction Instruction Code Name (Hex) RDCR 35 DIOR BB 4DIOR BC DOR 3B 4DOR 3C DDRDIOR BD 4DDRDIOR BE DDRQIOR ED DDRQIOR4 EE ...
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CS# SCK Phase Instruction 10.7.2 OTP Read (OTPR 4Bh): The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits ...
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The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same manner as any other programming operation. CS# input must be driven to the logic high state after the ...
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DYB Read (DYBRD E0h) The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used ...
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location must be read with a separate PPB Read command. The maximum operating clock frequency for the PPB Read command is 133 MHz. CS# SCK Phase 10.8.6 PPB Program (PPBP ...
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CS# SCK SI SO Phase 10.8.8 PPB Lock Bit Read (PLBRD A7h): The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO possible to read the PPB lock register ...
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the falling edge of the SCK signal possible to read the Password continuously by providing multiples of 64 clock cycles. The maximum operating clock frequency for the PASSRD command is 133 MHz. Figure 10.70 ...
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RESET# input low to initiate a hardware reset, in order to return the P_ERR and WIP bits to 0. This returns the device to standby state, ready for new commands such as a retry of the ...
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CS# SCK SI SO Phase June 13, 2012 S25FL512S_00_04 Figure 10.74 Mode Bit (MBR FFh) Reset Command Sequence ...
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Embedded Algorithm Performance Tables Symbol t WRR Write Time W t Page Programming (512 bytes) PP Sector Erase Time t SE (256-kB logical sectors = physical sectors) t Bulk Erase Time (S25FL512S) BE Notes: 1. ...
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... Read Dual Out (4-byte address) Data Learning Pattern Read OTP Program Program NV Data Learning Register Write Volatile Data Learning Register OTP Read Read Serial Flash Discoverable Parameters Bulk Erase Read Quad Out (3- or 4-byte address) Read Quad Out (4-byte address) Erase Suspend Erase Resume ...
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... The SFDP address space has a header starting at address zero that identifies the SFDP data structure and provides a pointer to each parameter. One parameter is mandated by the JEDEC JESD216 standard. Spansion provides an additional parameter by pointing to the ID-CFI address space i.e. the ID-CFI address space is a sub-set of the SFDP address space. The JEDEC parameter is located within the ID-CFI address space and is thus both a CFI parameter and an SFDP parameter ...
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... JEDEC parameter byte offset = 1120h = 448h Dword address 04h Parameter Table Pointer Byte 1 00h Parameter Table Pointer Byte 2 FFh Unused 01h Manufacturer ID (Spansion) 00h Parameter Minor Revision 01h Parameter Major Revision 51h Parameter Table Length (in double words = Dwords = 4 byte units) Parameter Table Pointer Byte 0 (Dword = 4 byte aligned) 00h Entry point for ID-CFI parameter is byte offset = 1000h relative to SFDP location zero ...
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... Table 11.4 Manufacturer and Device ID Data 01h Manufacturer ID for Spansion 02h (512 Mb) Device ID Most Significant Byte - Memory Interface Type 20h (512 Mb) Device ID Least Significant Byte - Density ID-CFI Length - number bytes following. Adding this value to the current location of 03h gives the address of the last valid location in the ID-CFI address map ...
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... Table 11.7 Device Geometry Definition for 512-Mbit Device Data 1Ah (512 Mb) Device Size = 2 02h Flash Device Interface Description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 01h 0004h = Single I/O SPI, 3-byte address 0005h = Multi I/O SPI, 3-byte address ...
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Byte Address 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 126 ...
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The Alternate Vendor-Specific Extended Query provides information related to the expanded command set provided by the FL-S family. The alternate query parameters use a format in which each parameter begins with an identifier byte and a ...
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... Parameter Length (The number of following bytes in this parameter. Adding this value to the 10h current location value +1 = the first byte of the next parameter) 53h ASCII “S” for manufacturer (Spansion) 32h ASCII “25” for Product Characters (Single Die SPI) 35h 46h ASCII “ ...
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Table 11.12 CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Table 11.13 CFI Alternate Vendor-Specific Extended Query Parameter 88h Data ...
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Table 11.15 CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Sheet Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h ...
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Table 11.15 CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Sheet Parameter Relative Byte Address Offset 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh ...
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Table 11.16 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - HPLC DDR Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h ...
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Table 11.17 CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Sheet Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh ...
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Table 11.17 CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Sheet Parameter Relative Byte Address Offset 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h ...
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Table 11.18 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h ...
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... Volatile, Read only 0 Erase Error Volatile, Read only 0 Occurred 1 if CR1[3]=1, Volatile if CR1[3]=1, Block 0 when Non-Volatile if Protection shipped from CR1[3]=0 Spansion Write Enable Volatile 0 Latch Write in Volatile, Read only 0 Progress S25FL512S Description Registers on page 56 for the full Description 1 = Locks state of SRWD, BP, and configuration register ...
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Bits Field Name 7 LC1 6 LC0 5 TBPROT 4 RFU 3 BPNV 2 RFU 1 QUAD 0 FREEZE Bits Field Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 ES ...
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Bits Field Name RFU 8 RFU 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 PWDMLB 1 PSTMLB 0 RFU Note: 1. Default value depends on ordering part number, see Field Bits Name 63 to ...
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... Initial Delivery State The device is shipped from Spansion with non-volatile bits set as follows: The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh). The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh. ...
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... BGA package, 1.00 mm pitch Speed AG = 133 MHz MHz DDR Device Technology S = 0.065 µm MirrorBit Process Technology Density 512 = 512 Mbit Device Family S25FL Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory S25FL512S S25FL512S_00_04 June 13, 2012 ...
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... Option AG DP S25FL512S AG DP Note: 1. Example, S25FL512SAGMFI000 package marking would be FL512SAIF00 13. Contacting Spansion Obtain the latest list of company locations and contact information at: http://www.spansion.com/About/Pages/Locations.aspx June 13, 2012 S25FL512S_00_04 Valid Combinations Package and Model Number ...
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... AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V) table: corrected T Embedded Algorithm Performance Program and Erase Performance table: corrected T Tables Device ID and Common Flash Interface Updated table: CFI Alternate Vendor-Specific Extended Query Parameter 0 (ID-CFI) Address Map Revision 03 (May 2, 2012) Global Added 105°C updates ...
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... Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...