S25FL128SAGNFI003 Spansion, S25FL128SAGNFI003 Datasheet
S25FL128SAGNFI003
Specifications of S25FL128SAGNFI003
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S25FL128SAGNFI003 Summary of contents
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... CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL128S_256S_00 ...
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... The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “ ...
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... Status Register bits to control protection against program or erase of a contiguous range of sectors. – Hardware and software control options – Advanced Sector Protection (ASP) – Individual sector protection controlled by boot code or password Spansion ® MirrorBit Technology with Eclipse Architecture Core Supply Voltage: 2.7V to 3.6V ...
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Performance Summary Table 1.1 Maximum Read Rates with the Same Core and I/O Voltage (V Read Fast Read Dual Read Quad Read Table 1.2 Maximum Read Rates with Lower I/O Voltage (V Read Fast Read Dual Read Quad Read ...
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... Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 SOIC 16-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 WSON Package 7.3 FAB024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.4 FAC024 24-Ball BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Software Interface 8. Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2 Flash Memory Array 8.3 ID-CFI Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.4 OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 July 12, 2012 S25FL128S_256S_00_05 ...
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... Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.2 Device ID and Common Flash Interface (ID-CFI) Address Map . . . . . . . . . . . . . . . . . . . . . 133 11.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.4 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Ordering Information 12. Ordering Information FL128S and FL256S 149 13. Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 S25FL128S and S25FL256S S25FL128S_256S_00_05 July 12, 2012 ...
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Figures Figure 3.1 HOLD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 10.11 Write Registers (WRR) Command Sequence – 16 data bits . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 10.12 Write ...
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Figure 10.55 Quad 512-byte Page Program Command Sequence (3-byte Address, 32h or 38h 112 Figure 10.56 Quad 256-byte Page Program Command Sequence (3-byte Address, 32h or 38h 113 ...
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Tables Table 1.1 Maximum Read Rates with the Same Core and I/O Voltage (V Table 1.2 Maximum Read Rates with Lower I/O Voltage (V Table 1.3 Maximum Read Rates DDR (V Table 1.4 Typical Program and Erase Rates . . ...
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Table 11.2 Manufacturer and Device ...
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... Overview 2.1 General Description The Spansion S25FL128S and S25FL256S devices are flash non-volatile memory products using: MirrorBit technology - that stores two data bits in each memory array transistor Eclipse architecture - that dramatically improves program and erase performance process lithography This family of devices connect to a host system via a Serial Peripheral Interface (SPI) ...
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Migration Notes 2.2.1 Features Comparison The S25FL128S and S25FL256S devices are command set and footprint compatible with prior generation FL-K and FL-P families. Parameter Technology Node Architecture Release Date Density Bus Width Supply Voltage Normal Read Speed (SDR) Fast ...
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... DDR read commands for SIO, DIO, and QIO. Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced Sector Protection feature found in several other Spansion parallel interface NOR memory families. 14 ...
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... Specification bulletins provide information on temporary differences in feature description or parametric variance since the publication of the last full data sheet. Contact your local sales office for details. Obtain the latest list of company locations and contact information at: http://www.spansion.com/About/Pages/Locations.aspx July 12, 2012 S25FL128S_256S_00_05 All information transferred between the host system and memory during one period while CS# is low ...
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... Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal ...
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Address and Data Configuration Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the SI signal. Data may be sent back to the host serially on the Serial Output ...
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Serial Input (SI) / IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI ...
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The HOLD# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode. CS# SCLK HOLD# SI_or_IO_(during_input) Valid Input SO_or_IO_(internal) SO_or_IO_(external) 3.10 Core Voltage Supply ( the voltage ...
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... Do Not Use (DNU) A device internal signal may be connected to the package connector. The connection may be used by Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the signal and may be left unconnected in the host system or may be tied to V signal routing channels ...
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Signal Protocols 4.1 SPI Clock Modes 4.1.1 Single Data Rate (SDR) The S25FL128S and S25FL256S devices can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes. Mode 0 with Clock Polarity ...
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CPOL=0_CPHA=0_SCLK CPOL=1_CPHA=1_SCLK CS# Instruction Transfer_Phase SI Inst 4.2 Command Protocol All communication between the host system and S25FL128S and S25FL256S memory devices is in the form of units called commands. All commands begin with an instruction that selects ...
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... Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. All attempts to read the flash memory array during a program, erase write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation ...
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Command Sequence Examples CS# SCLK SI SO Phase CS# SCLK Phase CS# SCLK Phase CS# SCLK ...
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CS# SCLK IO0 IO1 Phase CS SCLK IO0 7 6 IO1 IO2 IO3 Phase CS SCLK IO0 IO1 Phase ...
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CS SCLK Phase CS SCLK IO0 7 IO1 Phase CS SCLK IO0 7 IO1 IO2 IO3 Phase Additional sequence diagrams, specific to each command, are provided in on page 72. 4.3 Interface States This section describes ...
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Interface State Hold Cycle Single Input Cycle Host to Memory Transfer Single Latency (Dummy) Cycle Single Output Cycle Memory to Host Transfer Dual Input Cycle Host to Memory Transfer Dual Latency (Dummy) Cycle Dual Output Cycle Memory to Host Transfer ...
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Power-On (Cold) Reset When the core voltage supply remains at or below the V the device will begin its Power On Reset (POR) process. POR continues until the end of t (Minimum) t the device does not react to ...
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... Dual Latency (Dummy) Cycle Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and HOLD# high ...
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... Quad Latency (Dummy) Cycle Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low. The host may drive the IO signals during these cycles or the host may leave the IO floating ...
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... DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high and CS# low ...
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Configuration Register Effects on the Interface The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the number of mode bit and latency cycles for each type of instruction. ...
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Electrical Specifications 5.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied (Note 1) IO Input voltage with respect to Ground (V Output Short Circuit Current Notes must always be less ...
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Input Signal Overshoot During DC conditions, input or I/O signals should remain equal to or between V transitions, inputs or I/Os may overshoot 2. 2. 5.3 Power-Up and Power-Down The device must ...
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Symbol V (min (cut-off (low (cut-off July 12, 2012 S25FL128S_256S_00_05 ...
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DC Characteristics Applicable within operating ranges. Symbol V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH I Input Leakage Current LI Output Leakage I LO Current Active Power ...
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Timing Specifications 6.1 Key to Switching Waveforms Input Valid at logic high or low Valid at logic high or low Symbol Output Valid at logic high or low Valid at logic high or low Input Levels V + 0.4V ...
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Capacitance Characteristics OUT Note: 1. For more information on capacitance, please consult the IBIS models. 6.3 Reset 6.3.1 Power-On (Cold) Reset The device executes a Power-On Reset (POR) process until a time delay of t moment ...
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... The RESET# input provides a hardware method of resetting the flash memory device to standby state. RESET# must be high for t When RESET# is driven low for at least a minimum period of time (t operation in progress, tri-states all outputs, and ignores all read/write commands for the duration of t The device resets the interface to standby state ...
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SDR AC Characteristics Table 6.4 AC Characteristics (Single Die Package, V Symbol SCK Clock Frequency for READ and 4READ F SCK, R instructions SCK Clock Frequency for single commands as F SCK, C shown in SCK Clock Frequency for ...
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Table 6.5 AC Characteristics (Single Die Package, V Symbol F SCK Clock Frequency for READ, 4READ instructions SCK SCK Clock Frequency for all others SCK SCK Clock Period SCK Clock High Time WH ...
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Input / Output Timing CS# SCK SI SO CS# SCK SI SO CS# SCLK IO MSB Figure 6.9 SPI Single Bit Input Timing tCSS tSU tHD MSB IN ...
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CS# SCLK HOLD# SI_or_IO_(during_input) SO_or_IO_(during_output) CS# tWPS WP# SCLK SI SO Phase July 12, 2012 S25FL128S_256S_00_05 Figure 6.12 Hold Timing tHLCH tHHCH tCHHL tCHHH Hold Condition Standard Use tHZ tLZ A ...
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DDR AC Characteristics Symbol F SCK Clock Frequency for DDR READ instruction SCK SCK Clock Period for DDR READ instruction SCK Clock Rise Time (slew rate) crt t Clock Fall Time (slew rate) cft t ...
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DDR Input Timing CS# SCK SI_or_IO SO 6.5.2 DDR Output Timing CS# SCK SI SO_or_IO July 12, 2012 S25FL128S_256S_00_05 Figure 6.14 SPI DDR Input Timing tCSS tHD tSU tHD tSU ...
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SCK IO0 IO1 IO2 IO3 IO_valid Note: 1. Data Valid calculation at 66 MHz (min) – 6.75 ns – 1.5 ns – 600 ps – – ...
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SOIC 16 Physical Diagram S03016 — 16-Lead Wide Plastic Small Outline Package (300-mil Body Width) July 12, 2012 S25FL128S_256S_00_05 S25FL128S and S25FL256S 47 ...
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WSON Package 7.2.1 WSON Connection Diagram Note: RESET# and V are pulled Figure 7.2 Leadless Package (WSON), Top View 8 CS# VCC SO/IO1 ...
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WSON Physical Diagram WNG008 — WSON 8-contact ( mm) No-Lead Package PACKAGE SYMBOL MIN 0.45 b 0.35 D2 4. 0.70 A1 0.00 K July 12, 2012 S25FL128S_256S_00_05 D ...
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FAB024 24-Ball BGA Package 7.3.1 Connection Diagram Note: Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use either package Figure ...
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Physical Diagram FAB024 — 24-ball Ball Grid Array ( mm) Package July 12, 2012 S25FL128S_256S_00_05 S25FL128S and S25FL256S 51 ...
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FAC024 24-Ball BGA Package 7.4.1 Connection Diagram Note: 1. Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use either package ...
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... SD/ SE 0.5/0.5 7.4.3 Special Handling Instructions for FBGA Packages Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. July 12, 2012 S25FL128S_256S_00_05 ...
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... The S25FL128S device supports the extended address features in the same way but in essence ignores bits any address because the main flash array only needs 24 bits of address. This enables simple migration from the 128-Mb density to higher density devices without changing the address handling aspects of software ...
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Table 8.2 S25FL256S Sector and Memory Address Map, Top 4-kbyte Sectors Sector Size (kbyte Table 8.3 S25FL256S Sector and Memory Address Map, Uniform 256-kbyte Sectors Sector Size (kbyte) 256 Table 8.4 S25FL128S Sector and Memory Address Map, Bottom ...
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... Figure 8.1, OTP Address Space on page 57 The OTP memory space is intended for increased system security. OTP values, such as the random number programmed by Spansion, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution. The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when set to 1 ...
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... Available for User Programming 3E0 to 3FF Available for User Programming S25FL128S and S25FL256S 16 Byte Random Number Byte 0 Contents Initial Delivery State (Hex) Number Spansion Programmed Random ... Number Number All bytes = FF ... All bytes = FF All bytes = FF All bytes = FF All bytes = FF All bytes = FF ...
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... The default state shown for each bit refers to the state after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit when the device is shipped from Spansion. Non-volatile bits have the same cycling (erase and program) endurance as the main flash array. ...
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... Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software- protected against program and erase commands. The BP bits are either volatile or non-volatile, depending on the state of the BP non-volatile bit (BPNV) in the configuration register. When one or more of the BP bits is set to 1, the relevant memory area is protected against program and erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to 0’ ...
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... Some read commands require additional latency cycles as the SCK frequency is increased. The following latency code tables provide different latency settings that are configured by Spansion. The High Performance versus the Enhanced High Performance settings are selected by the ordering part number. ...
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... When TBPARM is set the parameter block is at the Bottom of the array. TBPARM is OTP and set when it ships from Spansion. If TBPARM is programmed attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]) ...
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Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit - Quad mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not ...
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... Bank Register Write (BRWR 17h). The Bank Address register supplies additional high order bits of the main flash array byte boundary address for legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits of address (above A23) for all 3-byte address commands when EXTADD=0 ...
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ASP Register (ASPR) Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh). The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP) features. Bits Field Name 15 ...
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... The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data Learning Register (VDLR). When shipped from Spansion, the NVDLR value is 00h. Once programmed, the NVDLR cannot be reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR ...
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... Spansion Programmed Random Number Spansion standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number concatenated with the day and time of tester insertion. ...
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... The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT bit can be used to protect an address range of the main flash array from program and erase operations. The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register ...
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... PPB =”0” or its DYB = “0” Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it. When either bit is 0, the sector is protected from program and erase operations. The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection ...
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... Persistent Protection Bits The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related to each sector. When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time ...
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PPB Lock Bit (PPBL[0]) The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared locks all PPBs and when set allows the PPBs to be changed. The PLBWR ...
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... The password is all 1’s when shipped from Spansion located in its own memory space and is accessible through the use of the Password Program and Password Read commands. All 64-bit password combinations are valid as a password. The Password Mode, once programmed, prevents reading the 64-bit password and further password programming ...
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... Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. All attempts to read the flash memory array during a program, erase write cycle (embedded operations) are ignored. The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an embedded operation ...
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Following are some general signal relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of commands, see – The host always ...
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For backward compatibility to the 3-byte address instructions, the standard instructions can be used in conjunction with the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to 0 (following power up and hardware reset), ...
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... ABRD Register Access ABWR BRRD BRWR BRAC DLPRD PNVDLR WVDLR READ 4READ FAST_READ 4FAST_READ DDRFR 4DDRFR DOR 4DOR QOR Read Flash Array 4QOR DIOR 4DIOR DDRDIOR 4DDRDIOR QIOR 4QIOR DDRQIOR 4DDRQIOR 4PP QPP Program Flash QPP Array 4QPP PGSP PGRS July 12, 2012 S25FL128S_256S_00_05 ...
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... Table 10.2 S25FL128S and S25FL256S Command Set (sorted by function) (Sheet Command Function Name Erase Flash Array ERSP ERRS One Time Program Array OTPR DYBRD DYBWR PPBRD ASPRD Advanced Sector Protection PLBRD PLBWR PASSRD PASSP PASSU RESET Reset Reserved for Future Use ...
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... OTP, Block Protection, and Advanced Sector Protection There are commands to read and program a separate One TIme Programmable (OTP) array for permanent data such as a serial number. There are commands to control a contiguous group (block) of flash memory July 12, 2012 S25FL128S_256S_00_05 ...
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... There are commands to control which individual flash memory array sectors are protected from program and erase operations. 10.1.8 Reset There is a command to reset to the default conditions present after power on to the device. There is a command to reset (exit from) the Enhanced Performance Read Modes ...
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Identification Commands 10.2.1 Read Identification - REMS (Read_ID or REMS 90h) The READ_ID command identifies the Device Manufacturer ID and the Device ID. The command is also referred to as Read Electronic Manufacturer and device Signature (REMS). READ-ID (REMS) ...
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... Common Flash Interface (CFI) information. The manufacturer identification is assigned by JEDEC. The CFI structure is defined by JEDEC standard. The device identification and CFI values are assigned by Spansion. The JEDEC Common Flash Interface (CFI) specification defines a device information structure, which allows a vendor-specified software flash management program (driver used for entire families of flash devices. ...
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Figure 10.3 Read Electronic Signature (RES) Command Sequence CS SCK SI SO 10.3 Register Access Commands 10.3.1 Read Status Register-1 (RDSR1 05h) The Read Status Register-1 (RDSR1) command allows the Status Register-1 contents to be read from SO. ...
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Figure 10.5 Read Status Register-2 (RDSR2) Command CS SCK Instruction High Impedance SO 10.3.3 Read Configuration Register (RDCR 35h) The Read Configuration Register (RDCR) command allows the Configuration Register contents to ...
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... BAR[7]. BAR provides the high order addresses needed by devices having more than 128 Mbits (16 Mbytes), when using 3-byte address commands without extended addressing enabled (BAR[7] EXTADD = 0). Because this command is part of the addressing method and is not changing data in the flash memory, this command does not require the WREN command to precede it. ...
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CS# SCK SI SO 10.3.7 Write Registers (WRR 01h) The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and Configuration Register. Before the Write Registers (WRR) command can be accepted by the device, ...
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Figure 10.11 Write Registers (WRR) Command Sequence – 16 data bits SCK SI SO The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits to ...
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... Notes: 1. The Status Register originally shows 00h when the device is first shipped from Spansion to the customer. 2. Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP# becomes IO2; therefore, it cannot be utilized. The WRR command has an alternate function of loading the Bank Address Register if the command immediately follows a BRAC command ...
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CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte ...
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As part of the power up reset, hardware reset, or command reset process the AutoBoot feature automatically starts a read access from a pre-specified address. At the time the reset process is completed, the device is ready to deliver ...
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CS# SCK IO0 IO1 IO2 IO3 10.3.12 AutoBoot Register Read (ABRD 14h) The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO, least significant byte first, most significant bit of each ...
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When the ABWR cycle is completed, the Write Enable Latch (WEL) is set The maximum clock frequency for the ABWR command is 133 MHz. CS# SCK SI SO 10.3.14 Program ...
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Write VDLR (WVDLR 4Ah) Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, ...
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... Read Memory Array Commands Read commands for the main flash array provide many options for prior generation SPI compatibility or enhanced performance SPI: Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR). Some SDR commands transfer address one bit per rising edge of SCK and return data bits of data per rising edge of SCK. These are called Read or Fast Read for 1-bit data ...
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Read (Read 03h or 4READ 13h) The instruction 03h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 03h (ExtAdd=1) ...
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Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch) The instruction 0Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 0Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 0Ch is followed by a 4-byte address ...
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Dual Output Read (DOR 3Bh or 4DOR 3Ch) The instruction 3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 3Ch is followed by a 4-byte ...
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Quad Output Read (QOR 6Bh or 4QOR 6Ch) The instruction 6Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or 6Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or 6Ch is followed by a 4-byte ...
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Figure 10.32 Quad Output Read Command Sequence (4-byte Address, 6Ch or 6Bh [ExtAdd=1], LC=11b) CS SCLK Instruction IO0 IO1 IO2 IO3 10.4.5 Dual I/O Read (DIOR BBh or 4DIOR BCh) ...
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During the Dual I/O Enhanced High Performance Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is raised high the device will be released from Dual I/O Read Enhanced High Performance ...
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Figure 10.35 Dual I/O Read Command Sequence (4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b) CS SCLK 8 cycles Instruction IO0 IO1 CS# SCLK 4 cycles Data N IO0 ...
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Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through ...
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Figure 10.38 Continuous Quad I/O Read Command Sequence (3-byte Address), LC=00b CS# SCLK 2 cycles 2 cycles Data N Data N+1 IO0 IO1 IO2 IO3 ...
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Figure 10.40 Continuous Quad I/O Read Command Sequence (4-byte Address), LC=00b CS# SCLK 2 cycles 2 cycles Data N Data N+1 IO0 IO1 IO2 IO3 ...
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Figure 10.41 on page 103 bit SDR instruction sequence to reduce initial access time (improves XIP performance). The Mode bits control the length of the next DDR Fast Read operation through the inclusion or exclusion of the first byte instruction ...
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Figure 10.43 DDR Fast Read Initial Access (4-byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b) CS SCLK 8 cycles Instruction Note: 1. Example DLP of 34h (or ...
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Then the memory contents, at the address given, is shifted out DDR fashion, two bits at a time on each clock edge through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by ...
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PVT (process, voltage, temperature) of both the memory device and the host controller as well as any system level delays caused by flight time on the PCB. Although the data learning pattern (DLP) is programmable, the ...
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DDR Quad I/O Read (EDh, EEh) The Read DDR Quad I/O command improves throughput with four I/O signals - IO0-IO3 similar to the Quad I/O Read command but allows input of the address four bits on every ...
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The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to when the corresponding data value returns from the memory device. The host controller will skew ...
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... Note: 1. Example DLP of 34h (or 00110100). 10.5 Program Flash Array Commands 10.5.1 Program Granularity 10.5.1.1 Page Programming Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming command to move data from the buffer to the memory array. This sets an upper limit on the amount of data that can be programmed with a single programming command ...
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... The programming process is managed by the flash memory device internal control logic. After a programming command is issued, the programming operation status can be checked using the Read Status Register-1 command ...
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Figure 10.54 Page Program (4PP) Command Sequence (4-byte Address, 12h July 12, 2012 S25FL128S_256S_00_05 ...
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Quad Page Program (QPP 32h or 38h, or 4QPP 34h) The Quad-input Page Program (QPP) command allows bytes to be programmed in the memory (changing bits from 1 to 0). The Quad-input Page Program (QPP) command allows up to ...
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Figure 10.56 Quad 256-byte Page Program Command Sequence (3-byte Address, 32h or 38h) CS# SCK IO0 IO1 IO2 IO3 CS# 40 SCK IO0 4 IO1 5 IO2 6 IO3 7 * Byte 5 *MSB CS# SCK IO0 7 * IO1 ...
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CS# SCK IO0 IO1 IO2 IO3 CS# 48 SCK IO0 4 IO1 5 IO2 6 IO3 7 * Byte 5 *MSB 10.5.4 Program Suspend (PGSP 85h) and Resume (PGRS 8Ah) The Program Suspend command allows the system to interrupt a ...
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... SI. This will initiate the beginning of internal erase cycle, which involves the pre- programming and erase of the chosen sector of the flash memory array. If CS# is not driven high after the last bit of address, the sector erase operation will not be executed. ...
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Figure 10.61 Parameter Sector Erase Command Sequence (3-byte Address, 20h SCK SCK SI 10.6.2 Sector Erase (SE D8h or 4SE DCh) The Sector Erase (SE) command sets all bits in the addressed sector ...
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... Bulk Erase (BE 60h or C7h) The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations ...
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Erase Suspend and Resume Commands (ERSP 75h or ERRS 7Ah) The Erase Suspend command, allows the system to interrupt a sector erase operation and then read from or program data to, any other sector. Erase Suspend is valid only ...
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See Table 10.9, Erase Suspend AC Parameters on page ERS Figure 10.66 Erase Suspend Command Sequence CS# SCLK Erase ...
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Table 10.6 Commands Allowed During Program or Erase Suspend (Sheet Instruction Instruction Code Name (Hex) PGSP 4PP 12 PPBRD E2 QPP 32, 38 4QPP 34 4READ 13 RDCR 35 DIOR BB 4DIOR BC DOR ...
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CS# SCK SI CS# SCK SI 10.7.2 OTP Read (OTPR 4Bh) The OTP Read command reads data from the OTP region. The OTP region is 1024 bytes so, the address bits from A23 to A10 must be zero for this ...
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CS SCK Instruction MSB High Impedance SO 10.8.2 ASP Program (ASPP 2Fh) Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN) command must be ...
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DYB Read (DYBRD E0h) The instruction E0h is latched into SI by the rising edge of the SCK signal. Followed by the 32-bit address selecting location zero within the desired sector (note, the high order address bits not used ...
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CS# 0 SCK SI 7 10.8.5 PPB Read (PPBRD E2h) The instruction E2h is shifted into SI by the rising edges of the SCK signal, followed by the 32-bit address selecting location zero within the desired sector (note, the high ...
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SCK SI SO 10.8.7 PPB Erase (PPBE E4h) The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by the device, a Write Enable (WREN) command must be ...
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Figure 10.77 PPB Lock Register Read Command Sequence 0ns 50ns CS# SCLK Phase Instruction 10.8.9 PPB Lock Bit Write (PLBWR A6h) The PPB Lock Bit Write (PLBWR) command clears the PPB Lock Register to ...
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CS# SCK SI SO 10.8.11 Password Program (PASSP E8h) Before the Password Program (PASSP) command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device. After the Write Enable (WREN) command ...
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Password Unlock (PASSU E9h) The PASSU command is entered by driving CS# to the logic low state, followed by the instruction and the password data bytes on SI, least significant byte first, most significant bit of each byte first. ...
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CS# SCK SI 10.9.2 Mode Bit Reset (MBR FFh) The Mode Bit Reset (MBR) command can be used to return the device from continuous high performance read mode back to normal standby awaiting any new command. Because some device packages ...
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Embedded Algorithm Performance Tables Symbol t WRR Write Time W Page Programming (512 bytes Page Programming (256 bytes) Sector Erase Time (64-kB / 4-kB physical sectors) Sector Erase Time t (64 kB Top/Bottom: logical sector = 16 ...
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Software Interface Reference 11.1 Command Summary Table 11.1 S25FL128S and S25FL256S Instruction Set (sorted by instruction) (Sheet Instruction Command Name (Hex) 01 WRR READ 04 WRDI 05 RDSR1 06 WREN 07 RDSR2 0B ...
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Table 11.1 S25FL128S and S25FL256S Instruction Set (sorted by instruction) (Sheet Instruction Command Name (Hex) A6 PLBWR A7 PLBRD AB RES B9 BRAC BB DIOR BC 4DIOR BD DDRDIOR BE 4DDRDIOR 4SE E0 DYBRD ...
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... July 12, 2012 S25FL128S_256S_00_05 Table 11.2 Manufacturer and Device ID Data 01h Manufacturer ID for Spansion 20h (128 Mb) 02h (256 Mb) Device ID Most Significant Byte - Memory Interface Type 18h (128 Mb) 19h (256 Mb) Device ID Least Significant Byte - Density ID-CFI Length - number bytes following. Adding this value to the current location of 03h gives the address of the last valid location in the ID-CFI address map ...
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... FL-S 128 Mbit and 256-Mbit devices have either a hybrid sector architecture with thirty two 4-kB sectors and all remaining sectors of 64-kB or with uniform 256-kB sectors. Devices with the hybrid sector architecture are initially shipped from Spansion with the 4 kB sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1[2] may be programed to invert the sector map to place the 4-kB sectors at the top of the array address map ...
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... July 12, 2012 S25FL128S_256S_00_05 Data 18h (128 Mb) Device Size = 2 19h (256 Mb) 02h Flash Device Interface Description; 0000h = x8 only 0001h = x16 only 0002h = x8/x16 capable 0003h = x32 only 01h 0004h = Single I/O SPI, 3-byte address 0005h = Multi I/O SPI, 3-byte address ...
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Table 11.7 CFI Primary Vendor-Specific Extended Query (Sheet Byte Address 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h The Alternate Vendor-Specific Extended Query provides information related to the expanded command set provided by the FL-S family. The alternate ...
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... Parameter Length (The number of following bytes in this parameter. Adding this value to the 10h current location value +1 = the first byte of the next parameter) 53h ASCII “S” for manufacturer (Spansion) 32h ASCII “25” for Product Characters (Single Die SPI) 35h 46h ASCII “ ...
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Table 11.11 CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Table 11.12 CFI Alternate Vendor-Specific Extended Query Parameter 88h Data Protection Parameter Relative Byte ...
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Table 11.14 CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Sheet Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h ...
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Table 11.14 CFI Alternate Vendor-Specific Extended Query Parameter 90h - HPLC(SDR) (Sheet Parameter Relative Byte Address Offset 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h ...
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Table 11.15 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - HPLC DDR Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h ...
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Table 11.16 CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Sheet Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h ...
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Table 11.16 CFI Alternate Vendor-Specific Extended Query Parameter 90h - EHPLC (SDR) (Sheet Parameter Relative Byte Address Offset 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h ...
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Table 11.17 CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR Parameter Relative Byte Address Offset 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h ...
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... Volatile, Read only 0 Volatile, Read only 0 Occurred 1 if CR1[3]=1, Volatile if CR1[3]=1, Block 0 when Non-Volatile if Protection shipped from CR1[3]=0 Spansion Volatile 0 Latch Write in Volatile, Read only 0 Progress S25FL128S and S25FL256S Description Registers on page 58 for the full Description 1 = Locks state of SRWD, BP, and configuration register ...
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Bits Field Name 7 LC1 6 LC0 5 TBPROT 4 RFU 3 BPNV 2 TBPARM 1 QUAD 0 FREEZE Bits Field Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU Bits Field ...
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Bits Field Name RFU 8 RFU 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 PWDMLB 1 PSTMLB 0 RFU Note: 1. Default value depends on ordering part number, see Field Bits Name 63 to ...
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... Initial Delivery State The device is shipped from Spansion with non-volatile bits set as follows: The entire memory array is erased: i.e. all bits are set to 1 (each byte contains FFh). The OTP address space has the first 16 bytes programmed to a random number. All other bytes are erased to FFh. ...
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... BGA package, 1.00 mm pitch Speed AG = 133 MHz MHz DDR Device Technology S = 0.065 µm MirrorBit Process Technology Density 128 = 128 Mbit 256 = 256 Mbit Device Family S25FL Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory S25FL128S and S25FL256S 149 ...
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... Option S25FL128S or S25FL256S Note: 1. Example, S25FL256SAGMFI000 package marking would be FL256SAIF00 13. Contacting Spansion Obtain the latest list of company locations and contact information at: http://www.spansion.com/About/Pages/Locations.aspx 150 Valid Combinations Package and Model Number Packing Type Temperature 00, G0, R0 MFI, MFV ...
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... Added Note 3 and Note 4 to Table 10.7 to note shared performance values across other commands Updated the t_ESL Erase Suspend Latency maximum value from 40 µ µs Device ID and Common Flash Interface CFI Alternate Vendor-Specific Extended Query Parameter 9Ah - EHPLC DDR table: corrected the ...
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... Command Set Summary S25FL128S and S25FL256S Command Set (sorted by function) table: added note Updated CFI Alternate Vendor-Specific Extended Query Parameter 0 table Device ID and Common Flash Interface Updated CFI Alternate Vendor-Specific Extended Query Parameter 84h Suspend Commands table (ID-CFI) Address Map Updated CFI Alternate Vendor-Specific Extended Query Parameter 8Ch Reset Timing table ...
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... Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...