S25FL208K0RMFI043 Spansion, S25FL208K0RMFI043 Datasheet

Page 1

... S25FL208K 8-Mbit 3.0V Serial Flash Memory with Uniform 4 kB Sectors Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL208K_00 ...

Page 2

... The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “ ...

Page 3

... Publication Number S25FL208K_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.  ...

Page 4

Table of Contents Distinctive Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

Figures Figure 2.1 8-pin SOIC (150/208 mil ...

Page 6

Tables Table 3.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

... -Decoder and Control Logic Serial Interface SCK SI/IO0 SO Figure 2.1 8-pin SOIC (150/208 mil WP# 4 GND S25FL208K Flash M em ory Y- Decoder I/O Buffers and Data Latches VCC 8 7 HOLD# SCK 6 5 SI/IO0 7 ...

Page 8

Signal Descriptions Serial Data Input / Output (SI/IO0) The SPI Serial Data Input/Output (SI/IO0) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge ...

Page 9

... Temperature Range I Package Materials F Package Type M Speed 0R Device Technology K Density 208 = Device Family S25FL Spansion Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory Table 4.1 S25FL208K Valid Combinations S25FL208K Valid Combinations Package and Speed Option Temperature 0R MFI S25FL208K = Tray = Tube = 13” Tape and Reel ...

Page 10

Memory Organizations The memory is organized as:  1,048,576 bytes  Uniform Sector Architecture – 16 blocks – 256 sectors  4,098 pages (256 bytes each) Each page can be individually programmed (bits ...

Page 11

... The S25FL208K supports Dual Output Operation when using the “Fast Read with Dual Output” (3B hex) command. This feature allows data to be transferred from the Serial Flash at twice the rate possible with the standard SPI. This command can be used to quickly download code from Flash to RAM upon Power-up (Code-shadowing) or for applications that cache code-segments to RAM for execution ...

Page 12

... Block Protect Bits (BP3, BP2, BP1, BP0) are non-volatile read/write bits in the status register (R5, R4, R3, and R2) that define the main flash array area to be software protected against program and erase commands. When one or more of the BP bits is set to 1, the relevant memory area is protected against program and erase. The Chip Erase (CE) command can be executed only when the BP bits are cleared to 0’ ...

Page 13

the Write Status Register instruction is locked out while the WP# pin is low. When the WP# pin is high the Write Status Register instruction is allowed. 7. Write Protection Some basic protection ...

Page 14

Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle ...

Page 15

Command Byte1 Code Name Write Enable 06h write Disable 04h Read Status 05h Register Write Status 01h Register Read Data 03h Fast Read 0Bh Fast Read Dual 3Bh Output Page Program 02h Block Erase D8h (64 ...

Page 16

SCK SI/IO0 SO 8.2 Write Disable (04h) The Write Disable command device from accepting a write, program or erase command. The host system must first drive CS# low, write the WRDI ...

Page 17

SCK SI/IO0 High Im pedance SO *=M SB 8.4 Write Status Register (01h) The Write Status Register command allows the Status Register ...

Page 18

SCK SI/IO0 8.5 Read Data (03h) The Read Data command allows one more data bytes to be sequentially read from the memory. The command ...

Page 19

... SO and SI/IO0, instead of just SO. This allows data to be transferred from the S25FL208K at twice the rate of standard SPI devices. The Fast Read Dual Output command is ideal for quickly downloading code from the SPI flash to RAM upon power-up or for applications that cache code- segments to RAM for execution. ...

Page 20

Mode3 SCK Mode0 SI/IO0 SCK SI/IO0 SO *=M SB 8.8 Page Program (PP) (02h) The Page Program command allows up to 256 bytes of data to be programmed at previously erased ...

Page 21

SCK SI/IO0 SCK SI/IO0 *=M SB 8.9 Sector Erase (SE) (20h) The Sector ...

Page 22

... Chip Erase (CE) (C7h) The Chip Erase command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array. Before the CE command can be accepted by the device, a Write Enable command must be issued and decoded by the device, which sets the Write Enable Latch in the Status Register to enable any write operations. The command is initiated by driving the CS# pin low and shifting the command code “ ...

Page 23

The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase command will not be executed. After CS# is driven high, the self-timed Chip Erase ...

Page 24

ode 3 SCK M ode 0 SI/IO0 SO 8.13 Release Deep Power-down / Device ID (ABh) The Release from Deep Power-down / Device ID command is a multi-purpose command. The device requires the Release from Deep Power-down ...

Page 25

... ID command. The command is initiated by driving the CS# pin low and shifting the command code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Spansion (01h) and the Device ID are shifted out on the falling edge of SCK with most significant bit (MSB) first as shown in Figure 8 ...

Page 26

... The command is initiated by driving the CS# pin low and shifting the command code “9Fh”. The JEDEC assigned Manufacturer ID byte for Spansion (01h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of SCK with most significant bit (MSB) first as ...

Page 27

SCK SI/IO0 SCK SI/IO0 January 17, 2013 S25FL208K_00_06 ...

Page 28

Electrical Specifications 9.1 Power-up Timing in Parameter V (min) to CS# Low CC Time Delay Before Write Instruction Write Inhibit Threshold Voltage Notes: 1. The parameters ...

Page 29

9.2 Absolute Maximum Ratings Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated ...

Page 30

DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the AC Measurement Conditions in Table 9.6 on page 31, when relying ...

Page 31

Input Levels 0.8 Vcc 0.2 Vcc 9.6 AC Characteristics Symbol (Notes (1) CLH CLL (1) CRLH CRLL t (2) CLCH t (2) CHCL t SLCH t ...

Page 32

Symbol (Notes) t BP1 t BP2 ( (6) CE Notes: 1. Clock high + Clock low must be less than or equal to 1/f 2. Value guaranteed by design and/or characterization, not 100% ...

Page 33

CS# SCK SI/IO0 SO HO LD# January 17, 2013 S25FL208K_00_06 Figure 9.5 Hold Timing ...

Page 34

... THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. ...

Page 35

... THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE 0.457 OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF 0.241 MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP 0.203 AND BOTTOM OF THE PLASTIC BODY. 5. ...

Page 36

Revision History Section Revision 01 (October 31, 2011) Initial release Revision 02 (December 21, 2011) DC Characteristics Updated I Revision 03 (January 6, 2012) Distinctive Features Updated Standby Current value Revision 04 (May 24, 2012) Global Data Sheet designation ...

Page 37

... Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure ...