KSZ8841-16MVLI TR Micrel, KSZ8841-16MVLI TR Datasheet - Page 38

• Manufacturer Part Number: KSZ8841-16MVLI TR
• Description: Ethernet ICs Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free)
• Manufacturer: Micrel

Specifications of KSZ8841-16MVLI TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-128
• Mounting Style: SMD/SMT

The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal VLBUSN =
1. Both the system/host/memory and KSZ8841M are capable of inserting wait states. To set the system/host/memory to
insert a wait state, assert RDYRTNN signal. To set the KSZ8841M to insert a wait state, assert SRDYN signal.
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 4KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group of control
registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the
host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 3. The first word contains the control information
for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon
whether hardware CRC checksum generation is enabled.
Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,
thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR
register.
Since multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status of
the packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the
TX queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word
aligned. Each control word corresponds to one TX packet. Table 4 gives the transmit control word bit fields.
October 2007
Micrel, Inc.
4. The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de-
5. The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write
asserted on the leading edge of the strobe.
operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must
be held until RDYRTNN is asserted.
Bit
15
14-6
5-0
Description
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8841M sets the transmit interrupt after the present frame has
been transmitted.
Reserved.
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status
information in the transmit status register.
Packet Memory
Address Offset
0
2
4 - up
Table 4. Transmit Control Word Bit Fields
Table 3. Frame Format for Transmit Queue
Bit 15
2
Control Word
Byte Count
Transmit Packet Data
(maximum size is 1916)
nd
Byte
38
1
st
Bit 0
Byte
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6