LFX125EC-03FH516I Lattice, LFX125EC-03FH516I Datasheet - Page 51
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LFX125EC-03FH516I
Manufacturer Part Number
LFX125EC-03FH516I
Description
FPGA - Field Programmable Gate Array Use LFX125EC-03F516I
Manufacturer
Lattice
Datasheet
1.LFX125EB-04F256C.pdf
(115 pages)
Specifications of LFX125EC-03FH516I
Number Of Gates
139 K
Number Of Logic Blocks
1936
Number Of I/os
22
Operating Supply Voltage
2.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-516
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
135
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Lattice Semiconductor
ispXPGA Family Data Sheet
sysHSI Block Timing
Figure 24 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 24. Receive Data Eye Diagram Template (Differential)
Bit Time
V
THD
200 mV Differential
+/- 100 mV Single Ended
jt
eo
jt
TH
SIN
TH
jt
: Optimum Threshold Crossing Jitter
TH
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery
(CDR) portion of the ispXPGA SERDES receiver is its ability to filter incoming signal jitter that is below the clock
recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data
error free, with eye openings significantly less than that shown in Figure 24.
51
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