LFX125EC-03F256I Lattice, LFX125EC-03F256I Datasheet - Page 53

• Manufacturer Part Number: LFX125EC-03F256I
• Description: FPGA - Field Programmable Gate Array E-Series, 139K Gates, 160 I/O, ispJTAG, 1.8V, -3 Speed, IND
• Manufacturer: Lattice

Specifications of LFX125EC-03F256I

• Product Category: FPGA - Field Programmable Gate Array
• Number Of Gates: 139 K
• Number Of Logic Blocks: 1936
• Number Of I/os: 22
• Operating Supply Voltage: 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-256
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 450

Lattice Semiconductor
REFCLK and SS_CLKIN Timing
Serializer Timing
Deserializer Timing
t
t
t
t
t
t
t
t
t
t
t
t
1. Bt: Bit Time Period. High Speed Serial Bit Time.
2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
3. Internal timing for reference only.
f
eo
ber
t
t
t
1. Eye opening based on jitter frequency of 100KHz.
2. Lower frequency operation assumes maximum eye closure of 800ps.
3. Internal timing for reference only.
DREFCLK
JPPREFCLK
PWREFCLK
RFREFCLK
JPPSOUT
JPP8B10B
RFSOUT
COSOUT
SKTX
CKOSOUT
HSITXDDATAS
HSITXDDATAH
DSIN
HSIOUTVALIDPRE
HSIOUTVALIDPOST
DSIN
SIN
Symbol
sysCLOCK PLL BYPASS mode.
Symbol
Symbol
SOUT Peak-to-Peak Output Data Jitter
SOUT Peak-to-Peak Random Jitter
SOUT Peak-to-Peak Deterministic Jitter
SOUT Output Data Rise/Fall Time (20%,
80%)
REFCLK to SOUT Delay
Skew of SOUT with Respect to
SS_CLKOUT
SS_CLKOUT to bit0 of SOUT
TXD Data Setup Time
TXD Data Hold Time
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on One Link
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or
80% to 20%)
SIN Frequency Deviation from REFCLK
SIN Eye Opening Tolerance
Bit Error Rate
RXD, SYDT Valid Time Before RECCLK Fall-
ing Edge
RXD, SYDT Valid Time
After RECCLK Falling Edge
Bit 0 of SIN Delay to RXD Valid at RECCLK
Falling edge
2
Description
Description
Description
SS/8B10B
10B12B
8B10B
8B10B
Mode
LVDS
SS
SS
All
All
All
53
10B12B
8B10B/
Mode
f
800 Mbps w/K28.7-
800 Mbps w/K28.5+
Note 3
Note 3
All
All
All
All
All
CLK
10B12B
8B10B/
Mode
with no jitter
All
All
All
Condition
Conditions
Notes 1, 2
Note 3
Note 3
Random Jitter
100-200MHz
40-100MHz
Condition
ispXPGA Family Data Sheet
2Bt
t
t
RCP
RCP
1.5 t
2Bt
1Bt
4.5Bt + 3
1
Min
1.5
-100
0.45
Min
- t
1
1
/2 - 0.7
/2 - 0.7
RCP
+ 2
+ 2
SKTX
-100
+
Min
2
1
2Bt
2Bt
1Bt
1.5 t
4.5Bt + 15
1
Max
0.25
130
160
700
300
1.0
+ t
Max
10
1
1
100
Max
0.01
RCP
+10
+10
100
SKTX
-12
2
+
UIPP
UIPP
Units
UIPP
Unit
Unit
ppm
ppm
Bits
ps
ps
ps
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns