LFX125EC-03FN516I Lattice, LFX125EC-03FN516I Datasheet - Page 8

• Manufacturer Part Number: LFX125EC-03FN516I
• Description: FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTA G 1.8V -3 Spd I
• Manufacturer: Lattice

Specifications of LFX125EC-03FN516I

• Product Category: FPGA - Field Programmable Gate Array
• Rohs: yes
• Number Of Gates: 139 K
• Number Of I/os: 176
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-516
• Minimum Operating Temperature: - 40 C

Lattice Semiconductor
Figure 6. ispXPGA Wide Logic Generator
Configurable Sequential Element
There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in
implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch
or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the
register’s D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the
accompanying LUT is occupied.
Control Logic
The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the
various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX
with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or
complement form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common
4A
S3
SEL0
4B
XIN3
S2
SEL1
SEL3
SEL2
4D
S1
ZIN2
ZIN3
S0
COUT
WIN2
WIN3
XIN2
4C
YIN2
YIN3
8
WLGZ1
WLGY0
WLGY1
WLGX0
WLGX1
WLGZ0
WLGW0
WLGW1
ispXPGA Family Data Sheet