74VCX163245G Fairchild Semiconductor, 74VCX163245G Datasheet

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74VCX163245G

Manufacturer Part Number
74VCX163245G
Description
TXRX TRANSLAT 16BIT DUAL 54FBGA
Manufacturer
Fairchild Semiconductor
Series
74VCXr
Datasheet

Specifications of 74VCX163245G

Logic Function
Translator, 3-State
Number Of Bits
8
Input Type
Voltage
Output Type
Voltage
Number Of Channels
2
Number Of Outputs/channel
8
Differential - Input:output
No/No
Propagation Delay (max)
4.4ns
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-FBGA
Supply Voltage
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74VCX163245G
Manufacturer:
Fairchild Semiconductor
Quantity:
10 000
Part Number:
74VCX163245GX
Manufacturer:
Fairchild Semiconductor
Quantity:
10 000
Part Number:
74VCX163245GX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©2000 Fairchild Semiconductor Corporation
74VCX163245 Rev. 1.7
Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
74VCX163245
Low Voltage 16-Bit Dual Supply Translating
Transceiver with 3-STATE Outputs
Features
Note:
1. To ensure the high impedance state during power up
Ordering Information
Notes:
2. Ordering code “G” indicates Trays.
3. Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
74VCX163245G
74VCX163245MTD
Bidirectional interface between busses ranging from
1.65V to 3.6V
Supports Live Insertion and Withdrawal
Static Drive (I
– ±24mA @ 3.0V V
– ±18mA @ 2.3V V
– ±6mA @ 1.65V V
Uses patented Quiet Series™ noise/EMI reduction
circuitry
Functionally compatible with 74 series 16245
Latchup performance exceeds 300mA
ESD performance:
– Human Body Model 2000V
– Machine model 200V
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
or power down, OE
pull up resistor. The minimum value of the resistor is
determined by the current sourcing capability of the
driver.
Order Number
OH
(2)(3)
/I
OL
(3)
n
)
CC
CC
CC
should be tied to V
Package Number
BGA54A
MTD48
(1)
CCB
through a
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205,
5.5mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 6.1mm Wide
General Description
The VCX163245 is a dual supply, 16-bit translating
transceiver that is designed for 2 way asynchronous
communication between busses at different supply volt-
ages by providing true signal translation. The supply rails
consist of V
at 2.3V to 3.6V and V
rail operating at 1.65V to 2.7V. (V
or equal to V
supply design allows for translation from 1.8V to 2.5V
busses to busses at a higher potential, up to 3.3V.
The Transmit/Receive (T/R) input determines the direc-
tion of data flow. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable (OE)
input, when HIGH, disables both A and B Ports by plac-
ing them in a High-Z condition. The A Port interfaces
with the higher voltage bus (2.7V to 3.3V); The B Port
interfaces with the lower voltage bus (1.8V to 2.5V). Also
the VCX163245 is designed so that the control pins
(T/R
The 74VCX163245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed oper-
ation while maintaining low CMOS power dissipation.
n
, OE
n
) are supplied by V
CCA
Package Description
CCA
, which is a higher potential rail operating
for proper device operation). This dual
CCB
, which is the lower potential
CCB
.
CCB
must be less than
www.fairchildsemi.com
May 2007
tm

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74VCX163245G Summary of contents

Page 1

... Ordering Information Order Number Package Number (2)(3) 74VCX163245G (3) 74VCX163245MTD Notes: 2. Ordering code “G” indicates Trays. 3. Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Quiet Series™ trademark of Fairchild Semiconductor Corporation. ...

Page 2

... Connection Diagram Pin Assignment for TSSOP Logic Diagram ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 Pin Assignment for FBGA (Top Thru View) FBGA Pin Assignments T CCB GND GND GND CCB T Pin Descriptions Pin Description Names OE Output Enable Input (Active LOW) n T/R ...

Page 3

... Second, the T/R n Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 Inputs OE Outputs 2 L – ...

Page 4

... Free Air Operating Temperature Minimum Input Edge Rate, V Notes Absolute Maximum Rating must be observed Unused inputs or I/O pins must be held HIGH or LOW. They may not float. 6. Operation requires CCB ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 Parameter (4) ( (5) Parameter / 0.8V to 2.0V ...

Page 5

... CCA CCB per supply CCA CCB I Increase in I per Input T/R, OE Increase in I per Input ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 (1.65V < V 1.95V, 2.3V < V CCB V (V) V (V) Conditions CCB CCA 1.65–1.95 2.3–2.7 1.65–1.95 2.3–2.7 1.65– ...

Page 6

... CCA CCB per supply CCA CCB I Increase in I per Input T/R, OE, Increase in I per Input ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 (1.65V < V 1.95V, 3.0V < V CCB V (V) V (V) Conditions CCB CCA 1.65–1.95 3.0–3.6 1.65–1.95 3.0–3.6 1.65– ...

Page 7

... Quiescent Supply Current, CCA CCB per supply CCA CCB I Increase in I per Input T/R, OE Increase in I per Input ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 (2.3V < V 2.7V, 3.0V V CCB V (V) V (V) Conditions CCB CCA 2.3–2.7 3.0–3.6 2.3–2.7 3.0– ...

Page 8

... OL V Quiet Output Dynamic OLV Valley Quiet Output Dynamic OHV Valley Quiet Output Dynamic OHV Valley ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 T –40°C to +85° 1.65V to 1.95V, V 1.65V to 1.95V, CCB CCB V 2.3V to 2.7V V 3.0V to 3.6V CCA CCA Min. Max. ...

Page 9

... Figure 2. Waveform for Inverting and Non-inverting Functions t t 2.0 ns, 10 Figure 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic t t 2.0 ns, 10 ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 Conditions V 2.5V, V CCB CCA or V CCA/B V 2.5V, V CCB CCA or V ...

Page 10

... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 5. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 Package Number BGA54A 10 www.fairchildsemi.com ...

Page 11

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 6. 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide ©2000 Fairchild Semiconductor Corporation 74VCX163245 Rev. 1.7 Package Number MTD48 11 www.fairchildsemi.com ...

Page 12

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ ...

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