LCMXO2-256ZE-2SG32IES Lattice, LCMXO2-256ZE-2SG32IES Datasheet - Page 72
LCMXO2-256ZE-2SG32IES
Manufacturer Part Number
LCMXO2-256ZE-2SG32IES
Description
FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 1.2V engineering sample
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-256ZE-2SG32IES
Rohs
yes
Maximum Operating Frequency
125 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Minimum Operating Temperature
- 40 C
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MachXO2 Oscillator Output Frequency
MachXO2 Standby Mode Timing – ZE Devices
MachXO2 Standby Mode Timing – HC/HE Devices
f
t
t
t
1. Output Clock Period Jitter specified at 133MHz. The values for lower frequencies will be smaller UIPP. The typical value for 133MHz is 95ps
t
t
t
t
t
t
t
PWRDN
PWRUP
WSTDBY
MAX
DT
OPJIT
STABLEOSC
PWRDN
PWRUP
WSTDBY
BNDGAPSTBL
and for 2.08MHz the typical value is 1.54ns.
Symbol
Symbol
Symbol
1
Oscillator Output Frequency (Commercial Grade Devices,
0 to 85°C)
Oscillator Output Frequency (Industrial Grade Devices,
-40 to 100°C)
Output Clock Duty Cycle
Output Clock Period Jitter
STDBY Low to Oscillator Stable
USERSTDBY High to Stop
USERSTDBY Low to Power Up
USERSTDBY Pulse Width
USERSTDBY High to Stop
USERSTDBY Low to Power Up
USERSTDBY Pulse Width
USERSTDBY High to Bandgap Stable
USERSTDBY
BG, POR
Parameter
Parameter
Parameter
t
PWRDN
3-33
t
LCMXO2-1200U
LCMXO2-2000U
LCMXO2-1200
LCMXO2-2000
LCMXO2-4000
LCMXO2-7000
WSTDBY
LCMXO2-256
LCMXO2-640
LCMXO2-640U
LCMXO2-1200
LCMXO2-2000
LCMXO2-4000
LCMXO2-7000
LCMXO2-256
LCMXO2-640
Device
Device
All
All
All
All
All
USERSTDBY Mode
DC and Switching Characteristics
125.685
124.355
Min.
Min.
0.01
0.01
20
19
—
43
—
Min.
20
18
—
MachXO2 Family Data Sheet
t
PWRUP
0.012
Typ.
Typ.
0.05
133
133
50
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
140.315
141.645
Max
Max
0.02
0.1
13
50
15
57
—
Max
50
—
9
Units
Units
UIPP
MHz
MHz
Units
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
%
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
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