LCMXO2-1200HC-5MG132CR1 Lattice, LCMXO2-1200HC-5MG132CR1 Datasheet - Page 32
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO2-1200HC-5MG132CR1
Manufacturer Part Number
LCMXO2-1200HC-5MG132CR1
Description
FPGA - Field Programmable Gate Array 1280 LUTs 105 I/O 3.3V -5 Speed COM
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200HC-5MG132CR1
Rohs
yes
Number Of I/os
105
Maximum Operating Frequency
140.315 MHz
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
csBGA-132
Minimum Operating Temperature
0 C
Operating Supply Current
3.49 mA
Factory Pack Quantity
360
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-5MG132CR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 32 of 106
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Figure 2-20. Embedded Function Block Interface
Hardened I
Every MachXO2 device contains two I
two cores can be configured either as an I
cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it will be able to control other devices on the I
face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I
The I
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Clock stretching
• Up to 400 KHz data transfer speed
• General call support
• Interface to custom logic through 8-bit WISHBONE interface
2
C cores support the following functionality:
2
C IP Core
Routing
Logic/
Core
WISHBONE
Interface
PLL0
2
EFB
Configuration
C IP cores. These are the primary and secondary I
Embedded Function Block (EFB)
Logic
2
C master or as an I
PLL1
I
2
Timer/Counter
I
C (Secondary)
2-28
2
C (Primary)
Control
SPI
Power
2
UFM
C slave. The only difference between the two IP
MachXO2 Family Data Sheet
Indicates connection
through core logic/routing.
(Secondary)
I/Os for I
I/Os for I
I/Os for SPI
(Primary)
2
2
C
C
2
2
C IP cores. Either of the
C bus through the inter-
Architecture
2
C Master.
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