iCE65L04F-TCB132C Lattice, iCE65L04F-TCB132C Datasheet - Page 106

• Manufacturer Part Number: iCE65L04F-TCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 3520 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L04F-TCB132C

• Rohs: yes
• Number Of Gates: 3520
• Number Of Logic Blocks: 20
• Number Of I/os: 95
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 80 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 26 uA
• Factory Pack Quantity: 384


t
t
t
t
t
t
F
* = Applies after sending the synchronization pattern.
Symbol
iCE65 Ultra Low-Power mobileFPGA
Power Consumption Characteristics
iCE65 Power Estimator Spreadsheet
(2.42, 30-MAR-2012)
106
CR_SCK
SUSPISI
HDSPISI
SPISCKH
SPISCKL
SPISCKCYC
SPI_SCK
NOTE: The typical static current for I/O Banks 0, 1, 2, and the SPI bank is less than the accuracy of the device tester.
Symbol
I
I
Core Power
I/O Power
Power Estimator
I
CC32M
CC32K
CC0K
Table 60
Table 61
counters, measured with a 32.768 kHz and at 32.0 MHz. Low power (-L) at 1.0 V operation and high-performance
(-T) version at 1.2V operation is provided.
Table 62
measurable within the accuracy of the test environment. The PIOs in I/O Bank 3 use different circuitry and dissipate
a small amount of static current.
To estimate the power consumption for a specific application, please download and use the iCE65 Power Estimator
Spreadsheet our use the power estimator built into the iCEcube software.
Symbol
I
I
I
I
I
CCO_SPI
CCO_0
CCO_1
CCO_2
CCO_3
Description
CRESET_B
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
f ≤ 2.768
SPI_SI
From
f = 32.0
provides various timing specifications for the SPI peripheral mode interface.
shows the power consumed on the internal VCC supply rail when the device is filled with 16-bit binary
provides the static current by I/O bank. The typical current for I/O Banks 0, 1, 2 and the SPI bank is not
f =0,
MHz
Table 61:
kHz
I/O Bank 0
I/O Bank 1
I/O Bank 2
I/O Bank 3
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI_SCK
SPI Bank
SPI_SI
To
Grade
–L
–T
–L
–T
–L
–T
VCC Power Consumption for Device Filled with 16-Bit Binary Counters
Minimum time from a rising edge on CRESET_B until
the first SPI write operation, first SPI_SCK. During
this time, the iCE65 FPGA is clearing its internal
configuration memory
Setup time on SPI_SI before the rising SPI_SCK clock edge
Hold time on SPI_SI after the rising SPI_SCK clock edge
SPI_SCK clock High time
SPI_SCK clock Low time
SPI_SCK clock period*
Sustained SPI_SCK clock frequency*
1.0V
1.2V
1.0V
1.2V
1.0V
1.2V
VCC
Table 62: I/O Bank Static Current (f = 0 MHz)
Static current consumption per I/O bank.
f = 0 MHz. No PIO pull-up resistors
enabled. All inputs grounded. All
outputs driving Low.
Table 60: SPI Peripheral Mode Timing
Typical
Description
12
19
15
23
3
4
iCE65L01
Max.
Description
™
Family
Typical
26
43
31
50
7
8
iCE65L04
Max.
iCE65L04/08: 1.2
Lattice Semiconductor Corporation
iCE65L01: « 1
iC65L01
iC65L04
iC65L08
Typical
« 1
« 1
« 1
« 1
Typical
100
54
90
62
14
17
iCE65L08
Min.
1200
800
800
12
12
20
20
40
All Grades
1
www.latticesemi.com
Max
Max.
Max.
1,000
25
—
—
—
—
—
Units
Units
mA
µA
µA
µA
µA
µA
µA
µA
Units
MHz
µs
ns
ns
ns
ns
ns