MC100EPT26DTG ON Semiconductor, MC100EPT26DTG Datasheet
MC100EPT26DTG
Specifications of MC100EPT26DTG
Related parts for MC100EPT26DTG
MC100EPT26DTG Summary of contents
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MC100EPT26 3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8−lead ...
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LVTTL LVPECL BB (Top View) Figure 1. 8−Lead Pinout and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of ...
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Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Input Voltage Sink/Source Operating Temperature Range A T Storage Temperature Range stg q Thermal Resistance (Junction−to−Ambient) JA Thermal Resistance (Junction−to−Case ...
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Table 5. TTL OUTPUT DC CHARACTERISTICS Symbol Characteristic V Output HIGH Voltage OH V Output LOW Voltage OL I Power Supply Current CCH I Power Supply Current CCL I Output Short Circuit Current OS NOTE: Device will meet the specifications ...
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... Figure 3. TTL Output Loading Used for Device Evaluation ORDERING INFORMATION Device MC100EPT26D MC100EPT26DG MC100EPT26DR2 MC100EPT26DR2G MC100EPT26DT MC100EPT26DTG MC100EPT26DTR2 MC100EPT26DTR2G MC100EPT26MNR4 MC100EPT26MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. APPLICATION ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...
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K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...