LFE2-6E-7F256C Lattice, LFE2-6E-7F256C Datasheet - Page 80

• Manufacturer Part Number: LFE2-6E-7F256C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7F256C

• Number Of I/os: 190
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-256
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 450

Lattice Semiconductor
Signal Descriptions (Cont.)
TCK
TDI
TDO
VCCJ
Configuration Pads (Used during sysCONFIG)
CFG[2:0]
INITN
PROGRAMN
DONE
CCLK
BUSY/SISPI
CSN
CS1N
WRITEN
D[7:0]/SPID[0:7]
DOUT/CSON
DI/CSSPIN
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O
O
I
I
I
I
I
I
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
Power supply pin for JTAG Test Access Port.
Mode pins used to specify configuration mode values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
Configuration Clock for configuring an FPGA in sysCONFIG mode.
Read control command in SPI3 or SPIX mode.
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
Write Data on Parallel port (active low).
sysCONFIG Port Data I/O.
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in SPI/
SPIX modes.
4-2
Description
LatticeECP2 Family Data Sheet
Pinout Information