LFXP6C-3F256C Lattice, LFXP6C-3F256C Datasheet - Page 108
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP6C-3F256C
Manufacturer Part Number
LFXP6C-3F256C
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -3 Spd
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T144C.pdf
(130 pages)
Specifications of LFXP6C-3F256C
Number Of I/os
188
Maximum Operating Frequency
320 MHz
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-256
Minimum Operating Temperature
0 C
Factory Pack Quantity
450
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-3F256C
Manufacturer:
LATTICE
Quantity:
8
Company:
Part Number:
LFXP6C-3F256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)
Lattice Semiconductor
Number
Ball
H21
H22
G21
G22
H20
H19
H17
H18
D21
D22
G20
G19
G17
G18
C22
D19
D20
C20
K18
K19
K21
K20
F21
F22
E21
E22
F18
F19
F20
E20
E19
J21
J22
J20
J19
J17
J18
-
-
-
-
-
Function
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO1
PR20B
PR20A
PR19B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR10B
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
VCCJ
TDO
TMS
TCK
Ball
TDI
-
Bank Differential
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
-
-
-
-
-
-
LFXP15
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
C
C
C
T
T
C
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RUM0_PLLC_FB_A
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
VREF1_2
VREF2_2
Function
Dual
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4-49
Function
GNDIO2
GNDIO2
GNDIO2
GNDIO2
GNDIO1
PR20B
PR20A
PR19B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR10B
PT56A
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
VCCJ
TDO
TMS
TCK
Ball
TDI
Bank Differential
LatticeXP Family Data Sheet
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
-
-
-
-
-
LFXP20
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
C
C
C
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pinout Information
RUM0_PLLC_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_FB_A
RUM0_PLLT_IN_A
VREF1_2
Function
VREF2_2
Dual
DQS
DQS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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